diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 352fbb84e..81d8f5919 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -5872,7 +5872,10 @@ bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, R
 		}
 	}
 
-	return parse(sig, module, str);
+	if (!parse(sig, module, str))
+		return false;
+	sig.extend_u0(lhs.width_);
+	return true;
 }
 
 RTLIL::CaseRule::~CaseRule()
diff --git a/tests/sat/fminit_seq_width.ys b/tests/sat/fminit_seq_width.ys
new file mode 100644
index 000000000..b6cf66470
--- /dev/null
+++ b/tests/sat/fminit_seq_width.ys
@@ -0,0 +1,17 @@
+read_verilog -sv -formal <<EOF
+module counter(input clk, input [2:0] rst, output logic is_full);
+    logic [1:0] ctr;
+
+    always @(posedge clk)
+        if (rst)
+            ctr <= 0;
+        else
+            ctr <= ctr+1;
+
+    assign is_full = (ctr == 2'b11);
+endmodule
+EOF
+
+hierarchy -check -top counter
+prep -top counter
+fminit -seq rst 0,1,2'b11,2'sb11