diff --git a/CODEOWNERS b/CODEOWNERS index 4617c39bb..681854226 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -36,6 +36,7 @@ frontends/ast/ @widlarizer techlibs/intel_alm/ @Ravenslofty techlibs/gowin/ @pepijndevos techlibs/gatemate/ @pu-cc +techlibs/fabulous/ fpga.research.group@gmail.com # pyosys pyosys/* @donn diff --git a/techlibs/fabulous/CMakeLists.txt b/techlibs/fabulous/CMakeLists.txt index 53091e5d3..ff6c08a0d 100644 --- a/techlibs/fabulous/CMakeLists.txt +++ b/techlibs/fabulous/CMakeLists.txt @@ -30,12 +30,4 @@ yosys_pass(synth_fabulous DATA_DIR fabulous DATA_FILES - cells_map.v - prims.v - latches_map.v - ff_map.v - ram_regfile.txt - regfile_map.v - io_map.v - arith_map.v ) diff --git a/techlibs/fabulous/io_map.v b/techlibs/fabulous/io_map.v deleted file mode 100644 index d3736258c..000000000 --- a/techlibs/fabulous/io_map.v +++ /dev/null @@ -1,7 +0,0 @@ -module \$__FABULOUS_IBUF (input PAD, output O); - IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.PAD(PAD), .O(O), .T(1'b1)); -endmodule - -module \$__FABULOUS_OBUF (output PAD, input I); - IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.PAD(PAD), .I(I), .T(1'b0)); -endmodule diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 0074a52af..59358c07e 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -17,17 +17,16 @@ * */ -#include "kernel/register.h" #include "kernel/celltypes.h" -#include "kernel/rtlil.h" #include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct SynthPass : public ScriptPass -{ - SynthPass() : ScriptPass("synth_fabulous", "FABulous synthesis script") { } +struct SynthPass : public ScriptPass { + SynthPass() : ScriptPass("synth_fabulous", "FABulous synthesis script") {} void help() override { @@ -44,14 +43,6 @@ struct SynthPass : public ScriptPass log(" -auto-top\n"); log(" automatically determine the top of the design hierarchy\n"); log("\n"); - log(" -blif \n"); - log(" write the design to the specified BLIF file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); - log("\n"); - log(" -edif \n"); - log(" write the design to the specified EDIF file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); - log("\n"); log(" -json \n"); log(" write the design to the specified JSON file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); @@ -59,11 +50,20 @@ struct SynthPass : public ScriptPass log(" -lut \n"); log(" perform synthesis for a k-LUT architecture (default 4).\n"); log("\n"); - log(" -vpr\n"); - log(" perform synthesis for the FABulous VPR flow (using slightly different techmapping).\n"); + log(" -ff \n"); + log(" convert FFs to cell types via dfflegalize (can be specified multiple times).\n"); log("\n"); - log(" -plib \n"); - log(" use the specified Verilog file as a primitive library.\n"); + log(" -cells-map \n"); + log(" map luts to corresponding cells.\n"); + log("\n"); + log(" -arith-map \n"); + log(" mapping file for arithmetic operations.\n"); + log("\n"); + log(" -clkbuf-map \n"); + log(" insert clock buffers using clkbufmap and map to the specified Verilog file.\n"); + log("\n"); + log(" -multiplier-map \n"); + log(" convert multiplications to multiplier primitives and map to the specified Verilog file.\n"); log("\n"); log(" -extra-plib \n"); log(" use the specified Verilog file for extra primitives (can be specified multiple\n"); @@ -73,8 +73,9 @@ struct SynthPass : public ScriptPass log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n"); log(" times).\n"); log("\n"); - log(" -encfile \n"); - log(" passed to 'fsm_recode' via 'fsm'\n"); + log(" -extra-mlibmap \n"); + log(" use the provided library convert memory into hardware supported memory (can be specified\n"); + log(" multiple times).\n"); log("\n"); log(" -nofsm\n"); log(" do not run FSM optimization\n"); @@ -86,16 +87,9 @@ struct SynthPass : public ScriptPass log(" -carry \n"); log(" carry mapping style (none, half-adders, ...) default=none\n"); log("\n"); - log(" -noregfile\n"); - log(" do not map register files\n"); - log("\n"); - log(" -iopad\n"); - log(" enable automatic insertion of IO buffers (otherwise a wrapper\n"); - log(" with manually inserted and constrained IO should be used.)\n"); - log("\n"); - log(" -complex-dff\n"); - log(" enable support for FFs with enable and synchronous SR (must also be\n"); - log(" supported by the target fabric.)\n"); + log(" -noiopad\n"); + log(" disable I/O buffer insertion (useful for hierarchical or \n"); + log(" out-of-context flows).\n"); log("\n"); log(" -noflatten\n"); log(" do not flatten design after elaboration\n"); @@ -122,28 +116,25 @@ struct SynthPass : public ScriptPass log("\n"); } - string top_module, json_file, blif_file, plib, fsm_opts, memory_opts, carry_mode; - std::vector extra_plib, extra_map; + string top_module, json_file, fsm_opts, memory_opts, carry_mode, cells_map, arith_map, clkbuf_map, multiplier_map; + std::vector extra_plib, extra_map, extra_mlibmap; + std::vector> extra_ffs; - bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten; - int lut; + bool autotop, noalumacc, nofsm, noshare, noiopad, flatten; + int lut, multiplier_a_max, multiplier_b_max, multiplier_a_min, multiplier_b_min, multiplier_y_min; void clear_flags() override { top_module.clear(); - plib.clear(); autotop = false; lut = 4; - forvpr = false; noalumacc = false; nofsm = false; noshare = false; - iopad = false; - complexdff = false; + noiopad = false; carry_mode = "none"; flatten = true; json_file = ""; - blif_file = ""; } void execute(std::vector args, RTLIL::Design *design) override @@ -152,55 +143,73 @@ struct SynthPass : public ScriptPass clear_flags(); size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - if (args[argidx] == "-top" && argidx+1 < args.size()) { + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-top" && argidx + 1 < args.size()) { top_module = args[++argidx]; continue; } - if (args[argidx] == "-json" && argidx+1 < args.size()) { + if (args[argidx] == "-json" && argidx + 1 < args.size()) { json_file = args[++argidx]; continue; } - if (args[argidx] == "-blif" && argidx+1 < args.size()) { - blif_file = args[++argidx]; - continue; - } - if (args[argidx] == "-run" && argidx+1 < args.size()) { - size_t pos = args[argidx+1].find(':'); + if (args[argidx] == "-run" && argidx + 1 < args.size()) { + size_t pos = args[argidx + 1].find(':'); if (pos == std::string::npos) { run_from = args[++argidx]; run_to = args[argidx]; } else { run_from = args[++argidx].substr(0, pos); - run_to = args[argidx].substr(pos+1); + run_to = args[argidx].substr(pos + 1); } continue; } - if (args[argidx] == "-vpr") { - forvpr = true; - continue; - } if (args[argidx] == "-auto-top") { autotop = true; continue; } - if (args[argidx] == "-lut") { + if (args[argidx] == "-lut" && argidx + 1 < args.size()) { lut = atoi(args[++argidx].c_str()); continue; } - if (args[argidx] == "-plib" && argidx+1 < args.size()) { - plib = args[++argidx]; + if (args[argidx] == "-ff" && argidx + 2 < args.size()) { + string cell = args[++argidx]; + string init = args[++argidx]; + extra_ffs.push_back({cell, init}); continue; } - if (args[argidx] == "-extra-plib" && argidx+1 < args.size()) { + if (args[argidx] == "-cells-map" && argidx + 1 < args.size()) { + cells_map = args[++argidx]; + continue; + } + if (args[argidx] == "-arith-map" && argidx + 1 < args.size()) { + arith_map = args[++argidx]; + continue; + } + if (args[argidx] == "-clkbuf-map" && argidx + 1 < args.size()) { + clkbuf_map = args[++argidx]; + continue; + } + if (args[argidx] == "-multiplier-map" && argidx + 6 < args.size()) { + multiplier_map = args[++argidx]; + multiplier_a_max = atoi(args[++argidx].c_str()); + multiplier_b_max = atoi(args[++argidx].c_str()); + multiplier_a_min = atoi(args[++argidx].c_str()); + multiplier_b_min = atoi(args[++argidx].c_str()); + multiplier_y_min = atoi(args[++argidx].c_str()); + continue; + } + if (args[argidx] == "-extra-plib" && argidx + 1 < args.size()) { extra_plib.push_back(args[++argidx]); continue; } - if (args[argidx] == "-extra-map" && argidx+1 < args.size()) { + if (args[argidx] == "-extra-map" && argidx + 1 < args.size()) { extra_map.push_back(args[++argidx]); continue; } + if (args[argidx] == "-extra-mlibmap" && argidx + 1 < args.size()) { + extra_mlibmap.push_back(args[++argidx]); + continue; + } if (args[argidx] == "-nofsm") { nofsm = true; continue; @@ -221,19 +230,11 @@ struct SynthPass : public ScriptPass memory_opts += " -no-rw-check"; continue; } - if (args[argidx] == "-noregfile") { - noregfile = true; + if (args[argidx] == "-noiopad") { + noiopad = true; continue; } - if (args[argidx] == "-iopad") { - iopad = true; - continue; - } - if (args[argidx] == "-complex-dff") { - complexdff = true; - continue; - } - if (args[argidx] == "-carry") { + if (args[argidx] == "-carry" && argidx + 1 < args.size()) { carry_mode = args[++argidx]; if (carry_mode != "none" && carry_mode != "ha") log_cmd_error("Unsupported carry style: %s\n", carry_mode); @@ -260,16 +261,12 @@ struct SynthPass : public ScriptPass void script() override { - if (plib.empty()) - run(stringf("read_verilog %s -lib +/fabulous/prims.v", complexdff ? "-DCOMPLEX_DFF" : "")); - else - run("read_verilog -lib " + plib); - if (help_mode) { run("read_verilog -lib ", "(for each -extra-plib)"); - } else for (auto lib : extra_plib) { - run("read_verilog -lib " + lib); - } + } else + for (auto lib : extra_plib) { + run("read_verilog -lib " + lib); + } if (check_label("begin")) { if (top_module.empty()) { @@ -282,9 +279,7 @@ struct SynthPass : public ScriptPass run("proc"); } - - if (check_label("flatten", "(unless -noflatten)")) - { + if (check_label("flatten", "(unless -noflatten)")) { if (flatten) { run("check"); run("flatten"); @@ -294,7 +289,7 @@ struct SynthPass : public ScriptPass } if (check_label("coarse")) { - run("tribuf -logic"); + run("tribuf -logic"); run("deminout"); // synth pass @@ -312,6 +307,27 @@ struct SynthPass : public ScriptPass run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)"); else if (lut) run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut)); + if (help_mode || multiplier_map != "") { + run("wreduce t:$mul"); + if (help_mode) { + run("techmap -map +/mul2dsp.v -map -D DSP_A_MAXWIDTH= -D DSP_B_MAXWIDTH= " + "-D DSP_A_MINWIDTH= -D DSP_B_MINWIDTH= -D DSP_Y_MINWIDTH= " + "-D DSP_NAME=$__FABULOUS_MUL", + "(if -multiplier-map)"); + } else { + run(stringf("techmap -map +/mul2dsp.v -map %s -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d " + "-D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_Y_MINWIDTH=%d " + "-D DSP_NAME=$__FABULOUS_MUL", + multiplier_map.c_str(), multiplier_a_max, multiplier_b_max, multiplier_a_min, multiplier_b_min, + multiplier_y_min)); + } + run("select a:mul2dsp", " (if -multiplier-map)"); + run("setattr -unset mul2dsp", " (if -multiplier-map)"); + run("opt_expr -fine", " (if -multiplier-map)"); + run("wreduce", " (if -multiplier-map)"); + run("select -clear", " (if -multiplier-map)"); + run("chtype -set $mul t:$__soft_mul", "(if -multiplier-map)"); + } if (!noalumacc) run("alumacc", " (unless -noalumacc)"); if (!noshare) @@ -321,12 +337,13 @@ struct SynthPass : public ScriptPass run("opt_clean"); } - if (check_label("map_ram", "(unless -noregfile)")) { - // RegFile extraction - if (!noregfile) { - run("memory_libmap -lib +/fabulous/ram_regfile.txt"); - run("techmap -map +/fabulous/regfile_map.v"); - } + if (check_label("map_memory")) { + if (help_mode) { + run("memory_libmap -lib ", "(for each -extra-mlibmap)"); + } else + for (auto lib : extra_mlibmap) { + run("memory_libmap -lib " + lib); + } } if (check_label("map_ffram")) { @@ -335,32 +352,43 @@ struct SynthPass : public ScriptPass run("opt -undriven -fine"); } + if (check_label("map_arith")) { + if (help_mode) { + run("techmap -map -D ARITH_"); + } else if (!arith_map.empty()) { + run(stringf("techmap -map %s -D ARITH_%s", arith_map.c_str(), carry_mode.c_str())); + } + run("clean"); + } + if (check_label("map_gates")) { run("opt -full"); - run(stringf("techmap -map +/techmap.v -map +/fabulous/arith_map.v -D ARITH_%s", - help_mode ? "" : carry_mode.c_str())); + run("techmap -map +/techmap.v"); run("opt -fast"); } - if (check_label("map_iopad", "(if -iopad)")) { - if (iopad || help_mode) { - run("opt -full"); - run("iopadmap -bits -outpad $__FABULOUS_OBUF I:PAD -inpad $__FABULOUS_IBUF O:PAD " - "-toutpad IO_1_bidirectional_frame_config_pass ~T:I:PAD " - "-tinoutpad IO_1_bidirectional_frame_config_pass ~T:O:I:PAD A:top", "(skip if '-noiopad')"); - run("techmap -map +/fabulous/io_map.v"); - } + if (check_label("map_iopad", "(skip if -noiopad)") && !noiopad) { + run("opt -full"); + run("iopadmap -bits " + "-inpad $__FABULOUS_IBUF OUT:PAD " + "-outpad $__FABULOUS_OBUF IN:PAD " + "-toutpad $__FABULOUS_TBUF EN:IN:PAD " + "-tinoutpad $__FABULOUS_IOBUF EN:OUT:IN:PAD"); } - if (check_label("map_ffs")) { - if (complexdff) { - run("dfflegalize -cell $_DFF_P_ 0 -cell $_SDFF_PP?_ 0 -cell $_SDFFCE_PP?P_ 0 -cell $_DLATCH_?_ x", "with -complex-dff"); - } else { - run("dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x", "without -complex-dff"); + if (help_mode) { + run("dfflegalize -cell ...", "(for each -ff)"); + } else if (!extra_map.empty()) { + std::string dff_str = "dfflegalize"; + for (const auto &[cell, init] : extra_ffs) + dff_str += stringf(" -cell %s %s", cell, init); + run(dff_str); } - run("techmap -map +/fabulous/latches_map.v"); - run("techmap -map +/fabulous/ff_map.v"); + run("opt_merge"); + } + + if (check_label("map_extra")) { if (help_mode) { run("techmap -map ...", "(for each -extra-map)"); } else if (!extra_map.empty()) { @@ -369,6 +397,7 @@ struct SynthPass : public ScriptPass map_str += stringf(" -map %s", map); run(map_str); } + run("simplemap"); run("clean"); } @@ -378,27 +407,31 @@ struct SynthPass : public ScriptPass } if (check_label("map_cells")) { - if (!forvpr) - run(stringf("techmap -D LUT_K=%d -map +/fabulous/cells_map.v", lut)); + if (help_mode) { + run("techmap -D LUT_K= -map "); + } else if (!cells_map.empty()) { + run(stringf("techmap -D LUT_K=%d -map %s", lut, cells_map.c_str())); + } run("clean"); } + + if (check_label("map_clkbufs")) { + if (help_mode) { + run("clkbufmap -buf $__FABULOUS_GBUF OUT:IN", "(if -clkbuf-map )"); + run("techmap -map ", "(if -clkbuf-map )"); + } else if (clkbuf_map != "") { + run("clkbufmap -buf $__FABULOUS_GBUF OUT:IN"); + run(stringf("techmap -map %s", clkbuf_map)); + run("clean"); + } + } + if (check_label("check")) { run("hierarchy -check"); run("stat"); } - if (check_label("blif")) - { - if (!blif_file.empty() || help_mode) - { - run("opt_clean -purge"); - run(stringf("write_blif -attr -cname -conn -param %s", - help_mode ? "" : blif_file.c_str())); - } - } - - if (check_label("json")) - { + if (check_label("json")) { if (!json_file.empty() || help_mode) run(stringf("write_json %s", help_mode ? "" : json_file)); } diff --git a/techlibs/fabulous/arith_map.v b/tests/arch/fabulous/arith_map.v similarity index 98% rename from techlibs/fabulous/arith_map.v rename to tests/arch/fabulous/arith_map.v index 8cf5a234b..b27729f08 100644 --- a/techlibs/fabulous/arith_map.v +++ b/tests/arch/fabulous/arith_map.v @@ -36,7 +36,7 @@ wire [Y_WIDTH:0] CARRY; LUT4_HA #( .INIT(16'b0), .I0MUX(1'b1) -) carry_statrt ( +) carry_start ( .I0(), .I1(CI), .I2(CI), .I3(), .Ci(), .Co(CARRY[0]) @@ -62,3 +62,4 @@ assign X = AA ^ BB; endmodule `endif + diff --git a/tests/arch/fabulous/carry.ys b/tests/arch/fabulous/carry.ys index bba969d37..b0e723c75 100644 --- a/tests/arch/fabulous/carry.ys +++ b/tests/arch/fabulous/carry.ys @@ -1,7 +1,7 @@ read_verilog ../common/add_sub.v hierarchy -top top proc -equiv_opt -assert -map +/fabulous/prims.v synth_fabulous -carry ha # equivalency check +equiv_opt -assert -map prims.v synth_fabulous -carry ha -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-max 10 t:LUT4_HA diff --git a/techlibs/fabulous/cells_map.v b/tests/arch/fabulous/cells_map.v similarity index 90% rename from techlibs/fabulous/cells_map.v rename to tests/arch/fabulous/cells_map.v index e33e641a8..2329286f5 100644 --- a/techlibs/fabulous/cells_map.v +++ b/tests/arch/fabulous/cells_map.v @@ -8,11 +8,9 @@ module \$lut (A, Y); generate if (WIDTH == 1) begin LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0])); - end else if (WIDTH == 2) begin LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1])); - end else if (WIDTH == 3) begin LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2])); @@ -30,5 +28,3 @@ module \$lut (A, Y); end endgenerate endmodule - -module \$_DFF_P_ (input D, C, output Q); LUTFF _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C)); endmodule diff --git a/tests/arch/fabulous/complexflop.ys b/tests/arch/fabulous/complexflop.ys index 13f4522b9..c5f300284 100644 --- a/tests/arch/fabulous/complexflop.ys +++ b/tests/arch/fabulous/complexflop.ys @@ -25,7 +25,7 @@ EOT hierarchy -top top proc flatten -equiv_opt -assert -map +/fabulous/prims.v synth_fabulous -complex-dff # equivalency check +equiv_opt -assert -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DFFE_PP_ x -ff $_SDFF_PP?_ x -ff $_SDFFCE_PP?P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -extra-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/fabulous/counter.ys b/tests/arch/fabulous/counter.ys index d79b378a6..32647caae 100644 --- a/tests/arch/fabulous/counter.ys +++ b/tests/arch/fabulous/counter.ys @@ -15,7 +15,7 @@ EOT hierarchy -top top proc flatten -equiv_opt -assert -map +/fabulous/prims.v synth_fabulous # equivalency check +equiv_opt -assert -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/techlibs/fabulous/ff_map.v b/tests/arch/fabulous/ff_map.v similarity index 100% rename from techlibs/fabulous/ff_map.v rename to tests/arch/fabulous/ff_map.v diff --git a/tests/arch/fabulous/fsm.ys b/tests/arch/fabulous/fsm.ys index 5f7ae28dd..b00c8a388 100644 --- a/tests/arch/fabulous/fsm.ys +++ b/tests/arch/fabulous/fsm.ys @@ -3,7 +3,7 @@ hierarchy -top fsm proc flatten -equiv_opt -run :prove -map +/fabulous/prims.v synth_fabulous +equiv_opt -run :prove -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v async2sync miter -equiv -make_assert -flatten gold gate miter stat diff --git a/tests/arch/fabulous/io_map.v b/tests/arch/fabulous/io_map.v new file mode 100644 index 000000000..031bd4a35 --- /dev/null +++ b/tests/arch/fabulous/io_map.v @@ -0,0 +1,15 @@ +module \$__FABULOUS_IBUF (input PAD, output OUT); + IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.T(1'b1), .O(OUT), .PAD(PAD)); +endmodule + +module \$__FABULOUS_OBUF (output PAD, input IN); + IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.T(1'b0), .I(IN), .PAD(PAD)); +endmodule + +module \$__FABULOUS_TBUF (output PAD, output IN, output EN); + IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.T(!EN), .I(IN), .PAD(PAD)); +endmodule + +module \$__FABULOUS_IOBUF (inout PAD, output OUT, input IN, output EN); + IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.T(!EN), .I(IN), .O(OUT), .PAD(PAD)); +endmodule diff --git a/techlibs/fabulous/latches_map.v b/tests/arch/fabulous/latches_map.v similarity index 100% rename from techlibs/fabulous/latches_map.v rename to tests/arch/fabulous/latches_map.v diff --git a/tests/arch/fabulous/logic.ys b/tests/arch/fabulous/logic.ys index 730d9ab54..e5b4773e7 100644 --- a/tests/arch/fabulous/logic.ys +++ b/tests/arch/fabulous/logic.ys @@ -1,7 +1,7 @@ read_verilog ../common/logic.v hierarchy -top top proc -equiv_opt -assert -map +/fabulous/prims.v synth_fabulous # equivalency check +equiv_opt -assert -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-max 1 t:LUT1 diff --git a/techlibs/fabulous/prims.v b/tests/arch/fabulous/prims.v similarity index 98% rename from techlibs/fabulous/prims.v rename to tests/arch/fabulous/prims.v index d1c493080..dfb70dc85 100644 --- a/techlibs/fabulous/prims.v +++ b/tests/arch/fabulous/prims.v @@ -418,11 +418,13 @@ module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_e endmodule -`ifdef EQUIV -`define COMPLEX_DFF -`endif +module LUTFF(input CLK, D, output reg O); + initial O = 1'b0; + always @ (posedge CLK) begin + O <= D; + end +endmodule -`ifdef COMPLEX_DFF module LUTFF_E ( output reg O, input CLK, E, D @@ -484,4 +486,3 @@ module LUTFF_ESS ( O <= D; end endmodule -`endif // COMPLEX_DFF diff --git a/techlibs/fabulous/ram_regfile.txt b/tests/arch/fabulous/ram_regfile.txt similarity index 100% rename from techlibs/fabulous/ram_regfile.txt rename to tests/arch/fabulous/ram_regfile.txt diff --git a/tests/arch/fabulous/regfile.ys b/tests/arch/fabulous/regfile.ys index 8d1eedef0..191c596d7 100644 --- a/tests/arch/fabulous/regfile.ys +++ b/tests/arch/fabulous/regfile.ys @@ -10,7 +10,7 @@ module sync_sync(input clk, we, input [4:0] aw, aa, ab, input [3:0] wd, output r endmodule EOT -synth_fabulous -top sync_sync +synth_fabulous -top sync_sync -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -arith-map arith_map.v -cells-map cells_map.v -extra-map ff_map.v -extra-map latches_map.v -extra-mlibmap ram_regfile.txt -extra-map regfile_map.v cd sync_sync select -assert-count 1 t:RegFile_32x4 diff --git a/techlibs/fabulous/regfile_map.v b/tests/arch/fabulous/regfile_map.v similarity index 100% rename from techlibs/fabulous/regfile_map.v rename to tests/arch/fabulous/regfile_map.v diff --git a/tests/arch/fabulous/tribuf.ys b/tests/arch/fabulous/tribuf.ys index 0dcf1cbab..65305756b 100644 --- a/tests/arch/fabulous/tribuf.ys +++ b/tests/arch/fabulous/tribuf.ys @@ -4,7 +4,7 @@ proc tribuf flatten synth -equiv_opt -assert -map +/fabulous/prims.v -map +/simcells.v synth_fabulous -iopad # equivalency check +equiv_opt -assert -map prims.v -map +/simcells.v synth_fabulous -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v -extra-map io_map.v # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module select -assert-count 3 t:IO_1_bidirectional_frame_config_pass