mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
This commit is contained in:
Eddie Hung
commit
4df4a97ffa
8 changed files with 382 additions and 41 deletions
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@ -26,7 +26,9 @@ PRIVATE_NAMESPACE_BEGIN
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struct ShregmapTech
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{
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virtual ~ShregmapTech() { }
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virtual bool analyze(vector<int> &taps) = 0;
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virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {}
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virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {}
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virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0;
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virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
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};
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@ -54,7 +56,7 @@ struct ShregmapOptions
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struct ShregmapTechGreenpak4 : ShregmapTech
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{
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bool analyze(vector<int> &taps)
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bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/)
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{
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if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) {
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taps.clear();
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@ -91,6 +93,145 @@ struct ShregmapTechGreenpak4 : ShregmapTech
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}
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};
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struct ShregmapTechXilinx7 : ShregmapTech
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{
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dict<SigBit, std::tuple<Cell*,int,int>> sigbit_to_shiftx_offset;
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const ShregmapOptions &opts;
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ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {}
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virtual void init(const Module* module, const SigMap &sigmap) override
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{
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for (const auto &i : module->cells_) {
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auto cell = i.second;
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if (cell->type == "$shiftx") {
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if (cell->getParam("\\Y_WIDTH") != 1) continue;
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int j = 0;
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for (auto bit : sigmap(cell->getPort("\\A")))
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sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0);
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log_assert(j == cell->getParam("\\A_WIDTH").as_int());
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}
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else if (cell->type == "$mux") {
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int j = 0;
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for (auto bit : sigmap(cell->getPort("\\A")))
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sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++);
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j = 0;
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for (auto bit : sigmap(cell->getPort("\\B")))
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sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++);
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}
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}
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}
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virtual void non_chain_user(const SigBit &bit, const Cell *cell, IdString port) override
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{
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auto it = sigbit_to_shiftx_offset.find(bit);
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if (it == sigbit_to_shiftx_offset.end())
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return;
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if (cell) {
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if (cell->type == "$shiftx" && port == "\\A")
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return;
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if (cell->type == "$mux" && (port == "\\A" || port == "\\B"))
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return;
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}
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sigbit_to_shiftx_offset.erase(it);
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}
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virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) override
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{
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if (GetSize(taps) == 1)
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return taps[0] >= opts.minlen-1 && sigbit_to_shiftx_offset.count(qbits[0]);
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if (taps.back() < opts.minlen-1)
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return false;
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Cell *shiftx = nullptr;
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int group = 0;
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for (int i = 0; i < GetSize(taps); ++i) {
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auto it = sigbit_to_shiftx_offset.find(qbits[i]);
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if (it == sigbit_to_shiftx_offset.end())
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return false;
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// Check taps are sequential
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if (i != taps[i])
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return false;
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// Check taps are not connected to a shift register,
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// or sequential to the same shift register
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if (i == 0) {
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int offset;
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std::tie(shiftx,offset,group) = it->second;
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if (offset != i)
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return false;
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}
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else {
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Cell *shiftx_ = std::get<0>(it->second);
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if (shiftx_ != shiftx)
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return false;
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int offset = std::get<1>(it->second);
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if (offset != i)
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return false;
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int group_ = std::get<2>(it->second);
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if (group_ != group)
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return false;
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}
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}
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log_assert(shiftx);
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// Only map if $shiftx exclusively covers the shift register
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if (shiftx->type == "$shiftx") {
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if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
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return false;
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}
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else if (shiftx->type == "$mux") {
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if (GetSize(taps) != 2)
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return false;
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}
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else log_abort();
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return true;
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}
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virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override
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{
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const auto &tap = *taps.begin();
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auto bit = tap.second;
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auto it = sigbit_to_shiftx_offset.find(bit);
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log_assert(it != sigbit_to_shiftx_offset.end());
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auto newcell = cell->module->addCell(NEW_ID, "$__XILINX_SHREG_");
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newcell->set_src_attribute(cell->get_src_attribute());
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newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH"));
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newcell->setParam("\\INIT", cell->getParam("\\INIT"));
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newcell->setParam("\\CLKPOL", cell->getParam("\\CLKPOL"));
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newcell->setParam("\\ENPOL", cell->getParam("\\ENPOL"));
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newcell->setPort("\\C", cell->getPort("\\C"));
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newcell->setPort("\\D", cell->getPort("\\D"));
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if (cell->hasPort("\\E"))
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newcell->setPort("\\E", cell->getPort("\\E"));
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Cell* shiftx = std::get<0>(it->second);
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RTLIL::SigSpec l_wire, q_wire;
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if (shiftx->type == "$shiftx") {
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l_wire = shiftx->getPort("\\B");
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q_wire = shiftx->getPort("\\Y");
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shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
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}
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else if (shiftx->type == "$mux") {
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l_wire = shiftx->getPort("\\S");
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q_wire = shiftx->getPort("\\Y");
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shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
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}
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else log_abort();
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newcell->setPort("\\Q", q_wire);
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newcell->setPort("\\L", l_wire);
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return false;
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}
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};
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struct ShregmapWorker
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{
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Module *module;
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@ -113,8 +254,10 @@ struct ShregmapWorker
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for (auto wire : module->wires())
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{
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if (wire->port_output || wire->get_bool_attribute("\\keep")) {
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for (auto bit : sigmap(wire))
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for (auto bit : sigmap(wire)) {
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sigbit_with_non_chain_users.insert(bit);
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if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
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}
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}
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if (wire->attributes.count("\\init")) {
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@ -152,8 +295,10 @@ struct ShregmapWorker
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for (auto conn : cell->connections())
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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for (auto bit : sigmap(conn.second)) {
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sigbit_with_non_chain_users.insert(bit);
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if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first);
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}
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}
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}
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@ -258,7 +403,7 @@ struct ShregmapWorker
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if (taps.empty() || taps.back() < depth-1)
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taps.push_back(depth-1);
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if (opts.tech->analyze(taps))
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if (opts.tech->analyze(taps, qbits))
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break;
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taps.pop_back();
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@ -377,6 +522,9 @@ struct ShregmapWorker
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ShregmapWorker(Module *module, const ShregmapOptions &opts) :
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module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
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{
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if (opts.tech)
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opts.tech->init(module, sigmap);
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make_sigbit_chain_next_prev();
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find_chain_start_cells();
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@ -501,6 +649,12 @@ struct ShregmapPass : public Pass {
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clkpol = "pos";
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opts.zinit = true;
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opts.tech = new ShregmapTechGreenpak4;
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}
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else if (tech == "xilinx") {
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opts.init = true;
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opts.params = true;
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enpol = "any_or_none";
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opts.tech = new ShregmapTechXilinx7(opts);
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} else {
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argidx--;
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break;
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