mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-14 06:45:26 +00:00
Code Activity

Add two new Liberty test cases

Browse source
This commit is contained in:
Akash Levy 2024-10-05 01:33:56 -10:00
parent 654e92e04e
commit 4de5e718ed
6 changed files with 73 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

5
tests/liberty/liberty_define.lib.verilogsim.ok
View file

@ -1,5 +0,0 @@
module not_cell (A, Y);
input A;
output Y;
assign Y = !A[0]; // !A[0]
endmodule