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Add two new Liberty test cases

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This commit is contained in:
Akash Levy 2024-10-05 01:33:56 -10:00
parent 654e92e04e
commit 4de5e718ed
6 changed files with 73 additions and 3 deletions
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4
tests/liberty/busdef2.lib.verilogsim.ok Normal file
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@ -0,0 +1,4 @@
module not_cell (Y);
output Y;
assign Y = !A[0]; // !A[0]
endmodule