mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-13 17:41:17 +00:00
Code Activity

rtlil: note SigSpec only has one chunk in internal docs

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-11-10 12:08:35 +01:00
parent ee5b8a97b9
commit 4dac5cd1f8
1 changed files with 10 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

19
docs/source/yosys_internals/formats/rtlil_rep.rst
View file

@ -194,17 +194,18 @@ RTLIL::SigSpec
A "signal" is everything that can be applied to a cell port. I.e.
- | Any constant value of arbitrary bit-width
- | A bit from a wire (``RTLIL::SigBit``)
| 1em For example: ``mywire[24]``
- | A range of bits from a wire (wire variant of ``RTLIL::SigChunk``)
| 1em For example: ``mywire, mywire[15:8]``
- | Any constant value of arbitrary bit-width (``std::vector<RTLIL::State>>`` variant of ``RTLIL::SigChunk``)
| 1em For example: ``1337, 16'b0000010100111001, 1'b1, 1'bx``
- | All bits of a wire or a selection of bits from a wire
| 1em For example: ``mywire, mywire[24], mywire[15:8]``
- | Concatenations of the above
| 1em For example: ``{16'd1337, mywire[15:8]}``
The ``RTLIL::SigSpec`` data type is used to represent signals. The
``RTLIL::Cell`` object contains one ``RTLIL::SigSpec`` for each cell port.
The ``RTLIL::SigSpec`` data type is used to represent signals.
It contains a single ``RTLIL::SigChunk`` or a vector of ``RTLIL::SigBit``.
The ``RTLIL::Cell`` object contains one ``RTLIL::SigSpec`` for each cell port.
In addition, connections between wires are represented using a pair of
``RTLIL::SigSpec`` objects. Such pairs are needed in different locations.