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intel_alm: add additional ABC9 timings
This commit is contained in:
Dan Ravensloft
parent
eed05953f8
commit
4d9d90079c
5 changed files with 95 additions and 78 deletions
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@ -69,6 +69,14 @@
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`default_nettype none
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// Cyclone V LUT output timings (picoseconds):
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//
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// CARRY A B C D E F G
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// COMBOUT - 605 583 510 512 - 97 400 (LUT6)
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// COMBOUT - 602 583 457 510 302 93 483 (LUT7)
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// SUMOUT 368 1342 1323 887 927 - 785 -
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// CARRYOUT 71 1082 1062 866 813 - 1198 -
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(* abc9_lut=2, lib_whitebox *)
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module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
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@ -76,12 +84,12 @@ parameter [63:0] LUT = 64'h0000_0000_0000_0000;
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`ifdef cyclonev
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specify
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(A => Q) = 602;
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(B => Q) = 584;
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(A => Q) = 605;
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(B => Q) = 583;
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(C => Q) = 510;
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(D => Q) = 510;
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(E => Q) = 339;
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(F => Q) = 94;
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(D => Q) = 512;
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(E => Q) = 400;
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(F => Q) = 97;
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endspecify
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`endif
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`ifdef cyclone10gx
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@ -107,11 +115,11 @@ parameter [31:0] LUT = 32'h0000_0000;
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`ifdef cyclonev
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specify
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(A => Q) = 584;
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(A => Q) = 583;
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(B => Q) = 510;
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(C => Q) = 510;
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(D => Q) = 339;
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(E => Q) = 94;
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(C => Q) = 512;
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(D => Q) = 400;
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(E => Q) = 97;
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endspecify
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`endif
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`ifdef cyclone10gx
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@ -137,9 +145,9 @@ parameter [15:0] LUT = 16'h0000;
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`ifdef cyclonev
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specify
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(A => Q) = 510;
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(B => Q) = 510;
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(C => Q) = 339;
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(D => Q) = 94;
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(B => Q) = 512;
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(C => Q) = 400;
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(D => Q) = 97;
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endspecify
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`endif
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`ifdef cyclone10gx
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@ -164,8 +172,8 @@ parameter [7:0] LUT = 8'h00;
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`ifdef cyclonev
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specify
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(A => Q) = 510;
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(B => Q) = 339;
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(C => Q) = 94;
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(B => Q) = 400;
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(C => Q) = 97;
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endspecify
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`endif
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`ifdef cyclone10gx
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@ -188,8 +196,8 @@ parameter [3:0] LUT = 4'h0;
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`ifdef cyclonev
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specify
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(A => Q) = 339;
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(B => Q) = 94;
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(A => Q) = 400;
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(B => Q) = 97;
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endspecify
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`endif
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`ifdef cyclone10gx
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@ -209,7 +217,7 @@ module MISTRAL_NOT(input A, output Q);
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`ifdef cyclonev
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specify
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(A => Q) = 94;
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(A => Q) = 97;
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endspecify
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`endif
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`ifdef cyclone10gx
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@ -230,31 +238,33 @@ parameter LUT1 = 16'h0000;
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`ifdef cyclonev
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specify
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(A => SO) = 1283;
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(B => SO) = 1167;
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(C => SO) = 866;
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(D0 => SO) = 756;
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(D1 => SO) = 756;
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(CI => SO) = 355;
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(A => CO) = 950;
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(B => CO) = 1039;
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(C => CO) = 820;
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(D0 => CO) = 1006;
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(D1 => CO) = 1006;
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(CI => CO) = 23;
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(A => SO) = 1342;
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(B => SO) = 1323;
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(C => SO) = 927;
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(D0 => SO) = 887;
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(D1 => SO) = 785;
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(CI => SO) = 368;
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(A => CO) = 1082;
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(B => CO) = 1062;
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(C => CO) = 813;
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(D0 => CO) = 866;
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(D1 => CO) = 1198;
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(CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM)
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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(A => SO) = 644;
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(B => SO) = 477;
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(C => SO) = 416;
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(A => SO) = 644;
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(B => SO) = 477;
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(C => SO) = 416;
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(D0 => SO) = 380;
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(D1 => SO) = 431;
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(CI => SO) = 276;
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(A => CO) = 525;
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(B => CO) = 433;
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(C => CO) = 712;
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(A => CO) = 525;
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(B => CO) = 433;
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(C => CO) = 712;
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(D0 => CO) = 653;
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(D1 => CO) = 593;
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(CI => CO) = 16;
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@ -54,43 +54,44 @@
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//
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// Note: the DFFEAS primitive is mostly emulated; it does not reflect what the hardware implements.
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`ifdef cyclonev
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`define SYNCPATH 262
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`define SYNCSETUP 522
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`define COMBPATH 0
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`endif
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`ifdef cyclone10gx
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`define SYNCPATH 219
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`define SYNCSETUP 268
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`define COMBPATH 0
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`endif
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// fallback for when a family isn't detected (e.g. when techmapping for equivalence)
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`ifndef SYNCPATH
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`define SYNCPATH 0
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`define SYNCSETUP 0
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`define COMBPATH 0
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`endif
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(* abc9_box, lib_whitebox *)
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module MISTRAL_FF(
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input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA,
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output reg Q
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);
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`ifdef cyclonev
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specify
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if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = `SYNCPATH;
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if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = `SYNCPATH;
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if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = `SYNCPATH;
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if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 731;
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if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 890;
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if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 618;
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$setup(DATAIN, posedge CLK, `SYNCSETUP);
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$setup(ENA, posedge CLK, `SYNCSETUP);
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$setup(SCLR, posedge CLK, `SYNCSETUP);
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$setup(SLOAD, posedge CLK, `SYNCSETUP);
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$setup(SDATA, posedge CLK, `SYNCSETUP);
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$setup(DATAIN, posedge CLK, /* -196 */ 0);
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$setup(ENA, posedge CLK, /* -196 */ 0);
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$setup(SCLR, posedge CLK, /* -196 */ 0);
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$setup(SLOAD, posedge CLK, /* -196 */ 0);
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$setup(SDATA, posedge CLK, /* -196 */ 0);
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if (ACLR === 1'b0) (ACLR => Q) = `COMBPATH;
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if (ACLR === 1'b0) (ACLR => Q) = 282;
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endspecify
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`endif
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`ifdef cyclone10gx
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specify
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// TODO (long-term): investigate these numbers.
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// It seems relying on the Quartus Timing Analyzer was not the best idea; it's too fiddly.
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if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 219;
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if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 219;
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if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 219;
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$setup(DATAIN, posedge CLK, 268);
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$setup(ENA, posedge CLK, 268);
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$setup(SCLR, posedge CLK, 268);
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$setup(SLOAD, posedge CLK, 268);
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$setup(SDATA, posedge CLK, 268);
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if (ACLR === 1'b0) (ACLR => Q) = 0;
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endspecify
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`endif
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initial begin
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// Altera flops initialise to zero.
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@ -1,9 +1,10 @@
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(* abc9_box *)
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module MISTRAL_MUL27x27(input [26:0] A, input [26:0] B, output [53:0] Y);
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// TODO: Cyclone 10 GX timings; the below are for Cyclone V
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specify
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(A *> Y) = 4057;
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(B *> Y) = 4057;
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(A *> Y) = 3732;
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(B *> Y) = 3928;
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endspecify
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assign Y = $signed(A) * $signed(B);
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@ -13,9 +14,10 @@ endmodule
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(* abc9_box *)
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module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y);
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// TODO: Cyclone 10 GX timings; the below are for Cyclone V
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specify
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(A *> Y) = 4057;
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(B *> Y) = 4057;
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(A *> Y) = 3180;
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(B *> Y) = 3982;
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endspecify
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assign Y = $signed(A) * $signed(B);
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@ -25,9 +27,10 @@ endmodule
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(* abc9_box *)
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module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);
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// TODO: Cyclone 10 GX timings; the below are for Cyclone V
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specify
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(A *> Y) = 4057;
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(B *> Y) = 4057;
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(A *> Y) = 2818;
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(B *> Y) = 3051;
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endspecify
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assign Y = $signed(A) * $signed(B);
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@ -54,12 +54,17 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1
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reg [31:0] mem = 32'b0;
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// TODO
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// TODO: Cyclone 10 GX timings; the below timings are for Cyclone V
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specify
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$setup(A1ADDR, posedge CLK1, 0);
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$setup(A1DATA, posedge CLK1, 0);
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$setup(A1ADDR, posedge CLK1, 86);
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$setup(A1DATA, posedge CLK1, 86);
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$setup(A1EN, posedge CLK1, 86);
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(B1ADDR *> B1DATA) = 0;
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(B1ADDR[0] => B1DATA) = 487;
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(B1ADDR[1] => B1DATA) = 475;
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(B1ADDR[2] => B1DATA) = 382;
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(B1ADDR[3] => B1DATA) = 284;
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(B1ADDR[4] => B1DATA) = 96;
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endspecify
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always @(posedge CLK1)
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@ -47,10 +47,9 @@ proc
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-count 1 t:MISTRAL_ALUT5
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select -assert-count 2 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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select -assert-count 3 t:MISTRAL_ALUT5
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select -assert-count 1 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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design -load read
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@ -70,10 +69,9 @@ proc
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-count 2 t:MISTRAL_ALUT5
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select -assert-count 4 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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select -assert-none t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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design -load read
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