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intel_alm: add additional ABC9 timings

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This commit is contained in:
Dan Ravensloft 2020-07-21 13:58:38 +01:00
parent eed05953f8
commit 4d9d90079c
5 changed files with 95 additions and 78 deletions
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13
techlibs/intel_alm/common/mem_sim.v
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@ -54,12 +54,17 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1
reg [31:0] mem = 32'b0;
// TODO
// TODO: Cyclone 10 GX timings; the below timings are for Cyclone V
specify
$setup(A1ADDR, posedge CLK1, 0);
$setup(A1DATA, posedge CLK1, 0);
$setup(A1ADDR, posedge CLK1, 86);
$setup(A1DATA, posedge CLK1, 86);
$setup(A1EN, posedge CLK1, 86);
(B1ADDR *> B1DATA) = 0;
(B1ADDR[0] => B1DATA) = 487;
(B1ADDR[1] => B1DATA) = 475;
(B1ADDR[2] => B1DATA) = 382;
(B1ADDR[3] => B1DATA) = 284;
(B1ADDR[4] => B1DATA) = 96;
endspecify
always @(posedge CLK1)