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intel_alm: add additional ABC9 timings

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This commit is contained in:
Dan Ravensloft 2020-07-21 13:58:38 +01:00
parent eed05953f8
commit 4d9d90079c
5 changed files with 95 additions and 78 deletions
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15
techlibs/intel_alm/common/dsp_sim.v
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@ -1,9 +1,10 @@
(* abc9_box *)
module MISTRAL_MUL27x27(input [26:0] A, input [26:0] B, output [53:0] Y);
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 4057;
(B *> Y) = 4057;
(A *> Y) = 3732;
(B *> Y) = 3928;
endspecify
assign Y = $signed(A) * $signed(B);
@ -13,9 +14,10 @@ endmodule
(* abc9_box *)
module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y);
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 4057;
(B *> Y) = 4057;
(A *> Y) = 3180;
(B *> Y) = 3982;
endspecify
assign Y = $signed(A) * $signed(B);
@ -25,9 +27,10 @@ endmodule
(* abc9_box *)
module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 4057;
(B *> Y) = 4057;
(A *> Y) = 2818;
(B *> Y) = 3051;
endspecify
assign Y = $signed(A) * $signed(B);