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simlib.v: Add x-output tag

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Also a few extra cell help texts.
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Krystine Sherwin 2024-09-06 15:36:42 +12:00
parent ce6a7fe4fc
commit 4d84d7e69f
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1 changed files with 23 additions and 10 deletions
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33
techlibs/common/simlib.v
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@ -526,7 +526,13 @@ endgenerate
endmodule
// --------------------------------------------------------
//* ver 2
//* title Indexed part-select
//* group binary
//* tags x-output
//- Same as the `$shift` cell, but fills with 'x'.
//-
module \$shift (A, B, Y);
@ -559,7 +565,13 @@ endgenerate
endmodule
// --------------------------------------------------------
//* ver 2
//* title Variable shifter
//* group binary
//- Performs a right logical shift if the second operand is positive (or
//- unsigned), and a left logical shift if it is negative.
//-
module \$shiftx (A, B, Y);
@ -1204,12 +1216,12 @@ endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $div (A, B, Y)
//* ver 2
//* title Divider
//* group binary
//-
//- Division with truncated result (rounded towards 0).
//* tags x-output
//- This corresponds to the Verilog '/' operator, performing division and
//- truncating the result (rounding towards 0).
//-
module \$div (A, B, Y);
@ -1235,12 +1247,12 @@ endmodule
// --------------------------------------------------------
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
//- $mod (A, B, Y)
//* ver 2
//* title Modulo
//* group binary
//-
//- Modulo/remainder of division with truncated result (rounded towards 0).
//* tags x-output
//- This corresponds to the Verilog '%' operator, giving the module (or
//- remainder) of division and truncating the result (rounding towards 0).
//-
//- Invariant: $div(A, B) * B + $mod(A, B) == A
//-
@ -1561,6 +1573,7 @@ endmodule
// --------------------------------------------------------
//* group mux
//* tags x-output
module \$pmux (A, B, S, Y);