mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Treat $anyseq as input from FST

Browse source
This commit is contained in:
Miodrag Milanovic 2022-04-22 16:23:39 +02:00
parent 9c7deabf94
commit 4d80bc24c7
1 changed files with 21 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

21
passes/sat/sim.cc
View file

@ -804,6 +804,25 @@ struct SimInstance
return did_something; return did_something;
} }
void addAdditionalInputs(std::map<Wire*,fstHandle> &inputs)
{
for (auto cell : module->cells())
{
if (cell->type.in(ID($anyseq))) {
SigSpec sig_y= cell->getPort(ID::Y);
if (sig_y.is_wire()) {
Wire *wire = sig_y.as_wire();
fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
if (id==0)
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
inputs[wire] = id;
}
}
}
for (auto child : children)
child.second->addAdditionalInputs(inputs);
}
void setState(dict<int, std::pair<SigBit,bool>> bits, std::string values) void setState(dict<int, std::pair<SigBit,bool>> bits, std::string values)
{ {
for(auto bit : bits) { for(auto bit : bits) {
@ -1065,6 +1084,8 @@ struct SimWorker : SimShared
} }
} }
top->addAdditionalInputs(inputs);
uint64_t startCount = 0; uint64_t startCount = 0;
uint64_t stopCount = 0; uint64_t stopCount = 0;
if (start_time==0) { if (start_time==0) {