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synth_nexus: Initial implementation

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Signed-off-by: David Shah <dave@ds0.me>
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David Shah 2020-10-01 11:15:54 +01:00
parent f9ed9786bf
commit 4d584d9319
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tests/arch/nexus/lutram.ys Normal file
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read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
proc
memory -nomap
equiv_opt -run :prove -map +/nexus/cells_sim.v synth_nexus
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w1r
stat
select -assert-count 8 t:WIDEFN9
select -assert-count 16 t:LUT4
select -assert-count 8 t:DPR16X4
select -assert-count 36 t:FD1P3IX
select -assert-none t:DPR16X4 t:FD1P3IX t:WIDEFN9 t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D