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synth_nexus: Initial implementation

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Signed-off-by: David Shah <dave@ds0.me>
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David Shah 2020-10-01 11:15:54 +01:00
parent f9ed9786bf
commit 4d584d9319
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tests/arch/nexus/logic.ys Normal file
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read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:LUT4
select -assert-none t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D