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synth_nexus: Initial implementation

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2020-10-01 11:15:54 +01:00
parent f9ed9786bf
commit 4d584d9319
30 changed files with 12528 additions and 0 deletions
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18
tests/arch/nexus/blockram.ys Normal file
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read_verilog ../common/blockram.v
design -save read
# Check that we use the right dual and single clock variants
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp
synth_nexus -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 1 t:PDPSC16K
select -assert-none t:PDPSC16K t:INV t:IB t:OB t:VLO t:VHI %% t:* %D
design -reset
read_verilog blockram_dc.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp_dc
synth_nexus -top sync_ram_sdp_dc
cd sync_ram_sdp_dc
select -assert-count 1 t:PDP16K
select -assert-none t:PDP16K t:INV t:IB t:OB t:VLO t:VHI %% t:* %D