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synth_nexus: Initial implementation

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2020-10-01 11:15:54 +01:00
parent f9ed9786bf
commit 4d584d9319
30 changed files with 12528 additions and 0 deletions
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34
techlibs/nexus/lutrams_map.v Normal file
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module \$__NEXUS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
parameter [63:0] INIT = 64'b0;
parameter CLKPOL2 = 1;
input CLK1;
input [3:0] A1ADDR;
output [3:0] A1DATA;
input [3:0] B1ADDR;
input [3:0] B1DATA;
input B1EN;
wire wck;
generate
if (CLKPOL2)
assign wck = CLK1;
else
INV wck_inv_i (.A(CLK1), .Z(wck));
endgenerate
DPR16X4 #(
.INITVAL($sformatf("0x%08x", INIT))
) _TECHMAP_REPLACE_ (
.RAD(A1ADDR),
.DO(A1DATA),
.WAD(B1ADDR),
.DI(B1DATA),
.WCK(CLK1),
.WRE(B1EN)
);
endmodule