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synth_nexus: Initial implementation
Signed-off-by: David Shah <dave@ds0.me>
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David Shah
parent
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30 changed files with 12528 additions and 0 deletions
286
techlibs/nexus/cells_xtra.py
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286
techlibs/nexus/cells_xtra.py
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#!/usr/bin/env python3
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# Based on Xilinx cells_xtra.py; modified for Radiant's structure
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from argparse import ArgumentParser
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from io import StringIO
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from enum import Enum, auto
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import os.path
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import sys
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import re
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class Cell:
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def __init__(self, name, keep=False, port_attrs={}):
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self.name = name
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self.keep = keep
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self.port_attrs = port_attrs
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self.found = False
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class State(Enum):
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OUTSIDE = auto()
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IN_MODULE = auto()
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IN_OTHER_MODULE = auto()
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IN_FUNCTION = auto()
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IN_TASK = auto()
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devices = [
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("lifcl", [
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Cell("ACC54"),
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Cell("ADC"),
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Cell("ALUREG"),
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Cell("BB_ADC", keep=True),
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Cell("BB_CDR", keep=True),
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Cell("BB_I3C_A", keep=True),
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Cell("BFD1P3KX"),
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Cell("BFD1P3LX"),
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Cell("BNKREF18", keep=True),
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Cell("CONFIG_LMMI", keep=True),
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Cell("DCC"),
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Cell("DCS"),
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Cell("DDRDLL"),
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Cell("DELAYA"),
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Cell("DELAYB"),
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Cell("DIFFIO18", keep=True),
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Cell("DLLDEL"),
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Cell("DP16K_MODE"),
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Cell("DP16K"),
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Cell("DPHY", keep=True),
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Cell("DPSC512K"),
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Cell("DQSBUF"),
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Cell("EBR_CORE"),
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Cell("EBR"),
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Cell("ECLKDIV"),
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Cell("ECLKSYNC"),
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Cell("FBMUX"),
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Cell("FIFO16K_MODE"),
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Cell("FIFO16K"),
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Cell("GSR"),
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Cell("HSE"),
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Cell("I2CFIFO"),
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Cell("IDDR71"),
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Cell("IDDRX1"),
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Cell("IDDRX2DQ"),
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Cell("IDDRX2"),
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Cell("IDDRX4DQ"),
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Cell("IDDRX4"),
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Cell("IDDRX5"),
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Cell("IFD1P3BX"),
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Cell("IFD1P3DX"),
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Cell("IFD1P3IX"),
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Cell("IFD1P3JX"),
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Cell("JTAG", keep=True),
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Cell("LRAM"),
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Cell("M18X36"),
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Cell("MIPI"),
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Cell("MULT18"),
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Cell("MULT18X18"),
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Cell("MULT18X36"),
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Cell("MULT36"),
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Cell("MULT36X36"),
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Cell("MULT9"),
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Cell("MULT9X9"),
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Cell("MULTADDSUB18X18"),
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Cell("MULTADDSUB18X18WIDE"),
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Cell("MULTADDSUB18X36"),
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Cell("MULTADDSUB36X36"),
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Cell("MULTADDSUB9X9WIDE"),
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Cell("MULTIBOOT", keep=True),
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Cell("MULTPREADD18X18"),
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Cell("MULTPREADD9X9"),
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Cell("ODDR71"),
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Cell("ODDRX1"),
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Cell("ODDRX2DQS"),
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Cell("ODDRX2DQ"),
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Cell("ODDRX2"),
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Cell("ODDRX4DQS"),
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Cell("ODDRX4DQ"),
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Cell("ODDRX4"),
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Cell("ODDRX5"),
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Cell("OFD1P3BX"),
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Cell("OFD1P3DX"),
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Cell("OFD1P3IX"),
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Cell("OFD1P3JX"),
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Cell("OSC"),
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Cell("OSCA"),
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Cell("OSHX2"),
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Cell("OSHX4"),
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Cell("PCIE"),
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Cell("PCLKDIV"),
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Cell("PCLKDIVSP"),
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Cell("PDP16K_MODE"),
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Cell("PDP16K"),
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Cell("PDPSC16K_MODE"),
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Cell("PDPSC16K"),
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Cell("PDPSC512K"),
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Cell("PLL"),
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Cell("PREADD9"),
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Cell("PUR", keep=True),
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Cell("REFMUX"),
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Cell("REG18"),
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Cell("SEDC", keep=True),
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Cell("SEIO18"),
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Cell("SEIO33"),
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Cell("SGMIICDR"),
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Cell("SP16K_MODE"),
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Cell("SP16K"),
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Cell("SP512K"),
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Cell("TSALLA"),
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Cell("TSHX2DQS"),
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Cell("TSHX2DQ"),
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Cell("TSHX4DQS"),
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Cell("TSHX4DQ"),
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Cell("WDT", keep=True),
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Cell("ACC54_CORE"),
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Cell("ADC_CORE"),
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Cell("ALUREG_CORE"),
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Cell("BNKREF18_CORE"),
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Cell("BNKREF33_CORE"),
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Cell("DIFFIO18_CORE"),
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Cell("CONFIG_CLKRST_CORE", keep=True),
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Cell("CONFIG_HSE_CORE", keep=True),
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Cell("CONFIG_IP_CORE", keep=True),
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Cell("CONFIG_JTAG_CORE", keep=True),
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Cell("CONFIG_LMMI_CORE", keep=True),
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Cell("CONFIG_MULTIBOOT_CORE", keep=True),
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Cell("CONFIG_SEDC_CORE", keep=True),
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Cell("CONFIG_WDT_CORE", keep=True),
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Cell("DDRDLL_CORE"),
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Cell("DLLDEL_CORE"),
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Cell("DPHY_CORE"),
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Cell("DQSBUF_CORE"),
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Cell("ECLKDIV_CORE"),
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Cell("ECLKSYNC_CORE"),
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Cell("FBMUX_CORE"),
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Cell("GSR_CORE"),
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Cell("I2CFIFO_CORE"),
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Cell("LRAM_CORE"),
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Cell("MULT18_CORE"),
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Cell("MULT18X36_CORE"),
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Cell("MULT36_CORE"),
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Cell("MULT9_CORE"),
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Cell("OSC_CORE"),
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Cell("PCIE_CORE"),
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Cell("PLL_CORE"),
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Cell("PREADD9_CORE"),
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Cell("REFMUX_CORE"),
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Cell("REG18_CORE"),
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Cell("SEIO18_CORE"),
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Cell("SEIO33_CORE"),
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Cell("SGMIICDR_CORE"),
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])
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]
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def xtract_cells_decl(device, cells, dirs, outf):
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fname = os.path.join(dir, device + '.v')
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with open(fname) as f:
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state = State.OUTSIDE
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# Probably the most horrible Verilog "parser" ever written.
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cell = None
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for l in f:
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l, _, comment = l.partition('//')
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l = l.strip()
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if l.startswith("module "):
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cell_name = l[7:l.find('(')].strip()
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cell = None
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module_ports = []
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iopad_pin = set()
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if state != State.OUTSIDE:
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print('Nested modules in {}.'.format(fname))
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sys.exit(1)
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for c in cells:
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if c.name != cell_name:
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continue
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cell = c
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state = State.IN_MODULE
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if cell.keep:
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outf.write('(* keep *)\n')
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outf.write('module {} (...);\n'.format(cell.name))
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cell.found = True
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m = re.search(r'synthesis .*black_box_pad_pin="([^"]*)"', comment)
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if m:
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iopad_pin = set(m.group(1).split(","))
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if cell is None:
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state = State.IN_OTHER_MODULE
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elif l.startswith('task '):
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if state == State.IN_MODULE:
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state = State.IN_TASK
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elif l.startswith('function '):
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if state == State.IN_MODULE:
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state = State.IN_FUNCTION
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elif l == 'endtask':
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if state == State.IN_TASK:
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state = State.IN_MODULE
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elif l == 'endfunction':
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if state == State.IN_FUNCTION:
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state = State.IN_MODULE
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elif l == 'endmodule':
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if state == State.IN_MODULE:
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for kind, rng, port in module_ports:
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for attr in cell.port_attrs.get(port, []):
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outf.write(' (* {} *)\n'.format(attr))
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if port in iopad_pin:
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outf.write(' (* iopad_external_pin *)\n')
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if rng is None:
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outf.write(' {} {};\n'.format(kind, port))
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else:
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outf.write(' {} {} {};\n'.format(kind, rng, port))
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outf.write(l + '\n')
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outf.write('\n')
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elif state != State.IN_OTHER_MODULE:
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print('endmodule in weird place in {}.'.format(cell.name, fname))
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sys.exit(1)
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state = State.OUTSIDE
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elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
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if l.endswith((';', ',')):
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l = l[:-1]
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if ';' in l:
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print('Weird port line in {} [{}].'.format(fname, l))
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sys.exit(1)
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kind, _, ports = l.partition(' ')
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for port in ports.split(','):
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port = port.strip()
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if port.startswith('['):
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rng, port = port.split()
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else:
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rng = None
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module_ports.append((kind, rng, port))
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elif l.startswith('parameter ') and state == State.IN_MODULE:
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if l.endswith((';', ',')):
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l = l[:-1]
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while ' ' in l:
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l = l.replace(' ', ' ')
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if ';' in l:
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print('Weird parameter line in {} [{}].'.format(fname, l))
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sys.exit(1)
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outf.write(' {};\n'.format(l))
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if state != State.OUTSIDE:
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print('endmodule not found in {}.'.format(fname))
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sys.exit(1)
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for cell in cells:
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if not cell.found:
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print('cell {} not found in {}.'.format(cell.name, fname))
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if __name__ == '__main__':
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parser = ArgumentParser(description='Extract Lattice blackbox cell definitions from Radiant.')
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parser.add_argument('radiant_dir', nargs='?', default='/opt/lscc/radiant/2.0/')
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args = parser.parse_args()
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dirs = [
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os.path.join(args.radiant_dir, 'cae_library/synthesis/verilog/'),
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]
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for dir in dirs:
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if not os.path.isdir(dir):
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print('{} is not a directory'.format(dir))
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out = StringIO()
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for device, cells in devices:
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xtract_cells_decl(device, cells, dirs, out)
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with open('cells_xtra.v', 'w') as f:
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f.write('// Created by cells_xtra.py from Lattice models\n')
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f.write('\n')
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f.write(out.getvalue())
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