Merge pull request #5240 from rocallahan/verilog-sort

In the Verilog backend, only sort modules that we're going to emit.

backends/verilog/verilog_backend.cc

@@ -2612,7 +2612,7 @@ struct VerilogBackend : public Backend {
 		Pass::call(design, "clean_zerowidth");
 		log_pop();
 
-		design->sort();
+               design->sort_modules();
 
 		*f << stringf("/* Generated by %s */\n", yosys_maybe_version());
 
@@ -2625,6 +2625,7 @@ struct VerilogBackend : public Backend {
 				continue;
 			}
 			log("Dumping module `%s'.\n", module->name.c_str());
+			module->sort();
 			dump_module(*f, "", module);
 		}
 

kernel/rtlil.cc

@@ -1139,6 +1139,12 @@ void RTLIL::Design::sort()
 		it.second->sort();
 }
 
+void RTLIL::Design::sort_modules()
+{
+	scratchpad.sort();
+	modules_.sort(sort_by_id_str());
+}
+
 void RTLIL::Design::check()
 {
 #ifndef NDEBUG

kernel/rtlil.h

@@ -1368,6 +1368,7 @@ struct RTLIL::Design
 	std::string scratchpad_get_string(const std::string &varname, const std::string &default_value = std::string()) const;
 
 	void sort();
+	void sort_modules();
 	void check();
 	void optimize();