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Merging with official repo

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This commit is contained in:
Aman Goel 2018-07-04 15:14:28 -04:00
commit 4d343fc1cd
28 changed files with 1350 additions and 191 deletions
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68
passes/cmds/setundef.cc
View file

@ -23,6 +23,13 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
#define MODE_ZERO 0
#define MODE_ONE 1
#define MODE_UNDEF 2
#define MODE_RANDOM 3
#define MODE_ANYSEQ 4
#define MODE_ANYCONST 5
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -97,30 +104,32 @@ struct SetundefWorker
RTLIL::State next_bit()
{
if (next_bit_mode == 0)
if (next_bit_mode == MODE_ZERO)
return RTLIL::State::S0;
if (next_bit_mode == 1)
if (next_bit_mode == MODE_ONE)
return RTLIL::State::S1;
if (next_bit_mode == 2)
log_abort();
if (next_bit_mode == 4)
if (next_bit_mode == MODE_UNDEF)
return RTLIL::State::Sx;
// xorshift32
next_bit_state ^= next_bit_state << 13;
next_bit_state ^= next_bit_state >> 17;
next_bit_state ^= next_bit_state << 5;
log_assert(next_bit_state != 0);
if (next_bit_mode == MODE_RANDOM)
{
// xorshift32
next_bit_state ^= next_bit_state << 13;
next_bit_state ^= next_bit_state >> 17;
next_bit_state ^= next_bit_state << 5;
log_assert(next_bit_state != 0);
return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1;
return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1;
}
log_abort();
}
void operator()(RTLIL::SigSpec &sig)
{
if (next_bit_mode == 2) {
if (next_bit_mode == MODE_ANYSEQ || next_bit_mode == MODE_ANYCONST) {
siglist.push_back(&sig);
return;
}
@ -145,7 +154,7 @@ struct SetundefPass : public Pass {
log(" also set undriven nets to constant values\n");
log("\n");
log(" -expose\n");
log(" also expose undriven nets as inputs\n");
log(" also expose undriven nets as inputs (use with -undriven)\n");
log("\n");
log(" -zero\n");
log(" replace with bits cleared (0)\n");
@ -159,6 +168,9 @@ struct SetundefPass : public Pass {
log(" -anyseq\n");
log(" replace with $anyseq drivers (for formal)\n");
log("\n");
log(" -anyconst\n");
log(" replace with $anyconst drivers (for formal)\n");
log("\n");
log(" -random <seed>\n");
log(" replace with random bits using the specified integer als seed\n");
log(" value for the random number generator.\n");
@ -191,25 +203,31 @@ struct SetundefPass : public Pass {
}
if (args[argidx] == "-zero") {
got_value = true;
worker.next_bit_mode = 0;
worker.next_bit_mode = MODE_ZERO;
worker.next_bit_state = 0;
continue;
}
if (args[argidx] == "-one") {
got_value = true;
worker.next_bit_mode = 1;
worker.next_bit_mode = MODE_ONE;
worker.next_bit_state = 0;
continue;
}
if (args[argidx] == "-anyseq") {
got_value = true;
worker.next_bit_mode = 2;
worker.next_bit_mode = MODE_ANYSEQ;
worker.next_bit_state = 0;
continue;
}
if (args[argidx] == "-anyconst") {
got_value = true;
worker.next_bit_mode = MODE_ANYCONST;
worker.next_bit_state = 0;
continue;
}
if (args[argidx] == "-undef") {
got_value = true;
worker.next_bit_mode = 4;
worker.next_bit_mode = MODE_UNDEF;
worker.next_bit_state = 0;
continue;
}
@ -219,7 +237,7 @@ struct SetundefPass : public Pass {
}
if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) {
got_value = true;
worker.next_bit_mode = 3;
worker.next_bit_mode = MODE_RANDOM;
worker.next_bit_state = atoi(args[++argidx].c_str()) + 1;
for (int i = 0; i < 10; i++)
worker.next_bit();
@ -232,7 +250,10 @@ struct SetundefPass : public Pass {
if (expose_mode && !undriven_mode)
log_cmd_error("Option -expose must be used with option -undriven.\n");
if (!got_value)
log_cmd_error("One of the options -zero, -one, -anyseq, or -random <seed> must be specified.\n");
log_cmd_error("One of the options -zero, -one, -anyseq, -anyconst, or -random <seed> must be specified.\n");
if (init_mode && (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST))
log_cmd_error("The options -init and -anyseq / -anyconst are exclusive.\n");
for (auto module : design->selected_modules())
{
@ -419,7 +440,7 @@ struct SetundefPass : public Pass {
module->rewrite_sigspecs(worker);
if (worker.next_bit_mode == 2)
if (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST)
{
vector<SigSpec*> siglist;
siglist.swap(worker.siglist);
@ -436,7 +457,10 @@ struct SetundefPass : public Pass {
width++;
if (width > 0) {
sig.replace(cursor, module->Anyseq(NEW_ID, width));
if (worker.next_bit_mode == MODE_ANYSEQ)
sig.replace(cursor, module->Anyseq(NEW_ID, width));
else
sig.replace(cursor, module->Anyconst(NEW_ID, width));
cursor += width;
} else {
cursor++;

8
passes/cmds/stat.cc
View file

@ -142,7 +142,7 @@ struct statdata_t
}
}
void log_data()
void log_data(RTLIL::IdString mod_name, bool top_mod)
{
log(" Number of wires: %6d\n", num_wires);
log(" Number of wire bits: %6d\n", num_wire_bits);
@ -163,7 +163,7 @@ struct statdata_t
if (area != 0) {
log("\n");
log(" Chip area for this module: %f\n", area);
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area);
}
}
};
@ -275,7 +275,7 @@ struct StatPass : public Pass {
log("\n");
log("=== %s%s ===\n", RTLIL::id2cstr(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)");
log("\n");
data.log_data();
data.log_data(mod->name, false);
}
if (top_mod != NULL && GetSize(mod_stat) > 1)
@ -288,7 +288,7 @@ struct StatPass : public Pass {
statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0);
log("\n");
data.log_data();
data.log_data(top_mod->name, true);
}
log("\n");