From 55a3638c71229e2730e1d0f7340f6c9d4087522d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 15:01:45 -0700
Subject: [PATCH 01/59] Port from xc7mux branch

---
 backends/aiger/xaiger.cc | 146 +++++++++++++++++++++++++++++----------
 passes/cmds/stat.cc      |   3 +
 passes/techmap/abc9.cc   |  72 ++++++++++++++-----
 3 files changed, 167 insertions(+), 54 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index d3384e136..66ab3878e 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -212,6 +212,9 @@ struct XAigerWriter
 				continue;
 			}
 
+			RTLIL::Module* box_module = module->design->module(cell->type);
+			bool abc_box = box_module && box_module->attributes.count("\\abc_box_id");
+
 			for (const auto &c : cell->connections()) {
 				/*if (c.second.is_fully_const()) continue;*/
 				for (auto b : c.second.bits()) {
@@ -224,20 +227,33 @@ struct XAigerWriter
 							if (I != b)
 								alias_map[b] = I;
 							/*if (!output_bits.count(b))*/
+							if (abc_box)
 								co_bits.emplace_back(b, 0);
+							else if (b.wire) {
+								output_bits.insert(b);
+								if (!b.wire->port_input)
+									unused_bits.erase(b);
+							}
 						}
 					}
 					if (is_output) {
 						SigBit O = sigmap(b);
 						/*if (!input_bits.count(O))*/
+						if (abc_box)
 							ci_bits.emplace_back(O, 0);
+						else {
+							input_bits.insert(O);
+							if (!O.wire->port_output)
+								undriven_bits.erase(O);
+						}
 					}
 				}
 				if (!type_map.count(cell->type))
 					type_map[cell->type] = type_map.size()+1;
 			}
 
-			box_list.emplace_back(cell);
+			if (abc_box)
+				box_list.emplace_back(cell);
 			//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
 		}
 
@@ -537,49 +553,105 @@ struct XAigerWriter
 
 		f << "c";
 
-		std::stringstream h_buffer;
-		auto write_h_buffer = [&h_buffer](int i32) {
+		if (!box_list.empty()) {
+			std::stringstream h_buffer;
+			auto write_h_buffer = [&h_buffer](int i32) {
+				// TODO: Don't assume we're on little endian
+#ifdef _WIN32
+				int i32_be = _byteswap_ulong(i32);
+#else
+				int i32_be = __builtin_bswap32(i32);
+#endif
+				h_buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
+			};
+			int num_outputs = output_bits.size();
+			if (omode && num_outputs == 0)
+				num_outputs = 1;
+			write_h_buffer(1);
+			write_h_buffer(input_bits.size() + ci_bits.size());
+			write_h_buffer(num_outputs + co_bits.size());
+			write_h_buffer(input_bits.size());
+			write_h_buffer(num_outputs);
+			write_h_buffer(box_list.size());
+
+			RTLIL::Module *holes_module = nullptr;
+			holes_module = module->design->addModule("\\__holes__");
+
+			for (auto cell : box_list) {
+				int box_inputs = 0, box_outputs = 0;
+				int box_id = module->design->module(cell->type)->attributes.at("\\abc_box_id").as_int();
+				Cell *holes_cell = nullptr;
+				if (holes_module && !holes_module->cell(stringf("\\u%d", box_id)))
+					holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type);
+				RTLIL::Wire *holes_wire;
+				int num_inputs = 0;
+				for (const auto &c : cell->connections()) {
+					if (cell->input(c.first)) {
+						box_inputs += c.second.size();
+						if (holes_cell) {
+							holes_wire = holes_module->wire(stringf("\\i%d", num_inputs));
+							if (!holes_wire) {
+								holes_wire = holes_module->addWire(stringf("\\i%d", num_inputs));
+								holes_wire->port_input = true;
+							}
+							++num_inputs;
+							holes_cell->setPort(c.first, holes_wire);
+						}
+					}
+					if (cell->output(c.first)) {
+						box_outputs += c.second.size();
+						if (holes_cell) {
+							holes_wire = holes_module->addWire(stringf("\\%s.%s", cell->type.c_str(), c.first.c_str()));
+							holes_wire->port_output = true;
+							holes_cell->setPort(c.first, holes_wire);
+						}
+					}
+				}
+				write_h_buffer(box_inputs);
+				write_h_buffer(box_outputs);
+				write_h_buffer(box_id);
+				write_h_buffer(0 /* OldBoxNum */);
+			}
+
+			f << "h";
+			std::string buffer_str = h_buffer.str();
 			// TODO: Don't assume we're on little endian
 #ifdef _WIN32
-			int i32_be = _byteswap_ulong(i32);
+			int buffer_size_be = _byteswap_ulong(buffer_str.size());
 #else
-			int i32_be = __builtin_bswap32(i32);
+			int buffer_size_be = __builtin_bswap32(buffer_str.size());
 #endif
-			h_buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
-		};
-		int num_outputs = output_bits.size();
-		if (omode && num_outputs == 0)
-			num_outputs = 1;
-		write_h_buffer(1);
-		write_h_buffer(input_bits.size() + ci_bits.size());
-		write_h_buffer(num_outputs + co_bits.size());
-		write_h_buffer(input_bits.size());
-		write_h_buffer(num_outputs);
-		write_h_buffer(box_list.size());
-		int box_id = 0;
-		for (auto cell : box_list) {
-			int box_inputs = 0, box_outputs = 0;
-			for (const auto &c : cell->connections()) {
-				if (cell->input(c.first))
-					box_inputs += c.second.size();
-				if (cell->output(c.first))
-					box_outputs += c.second.size();
-			}
-			write_h_buffer(box_inputs);
-			write_h_buffer(box_outputs);
-			write_h_buffer(box_id++);
-			write_h_buffer(0 /* OldBoxNum */);
-		}
-		std::string h_buffer_str = h_buffer.str();
-		// TODO: Don't assume we're on little endian
+			f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
+			f.write(buffer_str.data(), buffer_str.size());
+
+			if (holes_module) {
+				holes_module->fixup_ports();
+
+				holes_module->design->selection_stack.emplace_back(false);
+				RTLIL::Selection& sel = holes_module->design->selection_stack.back();
+				sel.select(holes_module);
+
+				Pass::call(holes_module->design, "flatten; aigmap");
+
+				holes_module->design->selection_stack.pop_back();
+
+				std::stringstream a_buffer;
+				XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, false /*bmode*/);
+				writer.write_aiger(a_buffer, false /*ascii_mode*/, false /*miter_mode*/, false /*symbols_mode*/, false /*omode*/);
+
+				f << "a";
+				std::string buffer_str = a_buffer.str();
+				// TODO: Don't assume we're on little endian
 #ifdef _WIN32
-		int h_buffer_size_be = _byteswap_ulong(h_buffer_str.size());
+				int buffer_size_be = _byteswap_ulong(buffer_str.size());
 #else
-		int h_buffer_size_be = __builtin_bswap32(h_buffer_str.size());
+				int buffer_size_be = __builtin_bswap32(buffer_str.size());
 #endif
-		f << "h";
-		f.write(reinterpret_cast<const char*>(&h_buffer_size_be), sizeof(h_buffer_size_be));
-		f.write(h_buffer_str.data(), h_buffer_str.size());
+				f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
+				f.write(buffer_str.data(), buffer_str.size());
+				holes_module->design->remove(holes_module);
+			}
+		}
 
 		f << stringf("Generated by %s\n", yosys_version_str);
 	}
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index 54f4ea817..3909c4c8c 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -269,6 +269,9 @@ struct StatPass : public Pass {
 				if (mod->get_bool_attribute("\\top"))
 					top_mod = mod;
 
+			if (mod->attributes.count("\\abc_box_id"))
+				continue;
+
 			statdata_t data(design, mod, width_mode, cell_area);
 			mod_stat[mod->name] = data;
 
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 3c4919b1f..b14eef485 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -272,7 +272,7 @@ failed:
 void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
 		std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
 		bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
-		const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode)
+		const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file)
 {
 	module = current_module;
 	map_autoidx = autoidx++;
@@ -322,18 +322,29 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 	log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
 			module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
 
-	std::string abc_script = stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str());
+	std::string abc_script;
 
 	if (!liberty_file.empty()) {
 		abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
 		if (!constr_file.empty())
 			abc_script += stringf("read_constr -v %s; ", constr_file.c_str());
 	} else
-	if (!lut_costs.empty())
+	if (!lut_costs.empty()) {
 		abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
+		if (!box_file.empty())
+			abc_script += stringf("read_box -v %s; ", box_file.c_str());
+	}
+	else
+	if (!lut_file.empty()) {
+		abc_script += stringf("read_lut %s; ", lut_file.c_str());
+		if (!box_file.empty())
+			abc_script += stringf("read_box -v %s; ", box_file.c_str());
+	}
 	else
 		abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
 
+	abc_script += stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str());
+
 	if (!script_file.empty()) {
 		if (script_file[0] == '+') {
 			for (size_t i = 1; i < script_file.size(); i++)
@@ -345,11 +356,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 					abc_script += script_file[i];
 		} else
 			abc_script += stringf("source %s", script_file.c_str());
-	} else if (!lut_costs.empty()) {
-		bool all_luts_cost_same = true;
-		for (int this_cost : lut_costs)
-			if (this_cost != lut_costs.front())
-				all_luts_cost_same = false;
+	} else if (!lut_costs.empty() || !lut_file.empty()) {
+		//bool all_luts_cost_same = true;
+		//for (int this_cost : lut_costs)
+		//	if (this_cost != lut_costs.front())
+		//		all_luts_cost_same = false;
 		abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
 		//if (all_luts_cost_same && !fast_mode)
 		//	abc_script += "; lutpack {S}";
@@ -576,7 +587,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 					RTLIL::Cell *cell;
 					RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
 					RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
-					if (!lut_costs.empty()) {
+					if (!lut_costs.empty() || !lut_file.empty()) {
 						// ABC can return NOT gates that drive POs
 						if (a_bit.wire->port_input) {
 							// If it's a NOT gate that comes from a primary input directly
@@ -1004,7 +1015,7 @@ struct Abc9Pass : public Pass {
 		log("        file format).\n");
 		log("\n");
 		log("    -constr <file>\n");
-		log("        pass this file with timing constraints to ABC. use with -liberty.\n");
+		log("        pass this file with timing constraints to ABC. Use with -liberty.\n");
 		log("\n");
 		log("        a constr file contains two lines:\n");
 		log("            set_driving_cell <cell_name>\n");
@@ -1041,6 +1052,9 @@ struct Abc9Pass : public Pass {
 		log("        the area cost doubles with each additional input bit. the delay cost\n");
 		log("        is still constant for all lut widths.\n");
 		log("\n");
+		log("    -lut <file>\n");
+		log("        pass this file with lut library to ABC.\n");
+		log("\n");
 		log("    -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
 		log("        generate netlist using luts. Use the specified costs for luts with 1,\n");
 		log("        2, 3, .. inputs.\n");
@@ -1094,6 +1108,9 @@ struct Abc9Pass : public Pass {
 		log("        this attribute is a unique integer for each ABC process started. This\n");
 		log("        is useful for debugging the partitioning of clock domains.\n");
 		log("\n");
+		log("    -box <file>\n");
+		log("        pass this file with box library to ABC. Use with -lut.\n");
+		log("\n");
 		log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
 		log("loaded into ABC before the ABC script is executed.\n");
 		log("\n");
@@ -1123,7 +1140,7 @@ struct Abc9Pass : public Pass {
 #else
 		std::string exe_file = proc_self_dirname() + "yosys-abc";
 #endif
-		std::string script_file, liberty_file, constr_file, clk_str;
+		std::string script_file, liberty_file, constr_file, clk_str, box_file, lut_file;
 		std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
 		bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
 		bool show_tempdir = false, sop_mode = false;
@@ -1169,8 +1186,8 @@ struct Abc9Pass : public Pass {
 				continue;
 			}
 			if (arg == "-constr" && argidx+1 < args.size()) {
-				rewrite_filename(constr_file);
 				constr_file = args[++argidx];
+				rewrite_filename(constr_file);
 				if (!constr_file.empty() && !is_absolute_path(constr_file))
 					constr_file = std::string(pwd) + "/" + constr_file;
 				continue;
@@ -1199,8 +1216,17 @@ struct Abc9Pass : public Pass {
 					lut_mode = atoi(arg.substr(0, pos).c_str());
 					lut_mode2 = atoi(arg.substr(pos+1).c_str());
 				} else {
-					lut_mode = atoi(arg.c_str());
-					lut_mode2 = lut_mode;
+					pos = arg.find_first_of('.');
+					if (pos != string::npos) {
+						lut_file = arg;
+						rewrite_filename(lut_file);
+						if (!lut_file.empty() && !is_absolute_path(lut_file))
+							lut_file = std::string(pwd) + "/" + lut_file;
+					}
+					else {
+						lut_mode = atoi(arg.c_str());
+						lut_mode2 = lut_mode;
+					}
 				}
 				lut_costs.clear();
 				for (int i = 0; i < lut_mode; i++)
@@ -1357,11 +1383,18 @@ struct Abc9Pass : public Pass {
 				markgroups = true;
 				continue;
 			}
+			if (arg == "-box" && argidx+1 < args.size()) {
+				box_file = args[++argidx];
+				rewrite_filename(box_file);
+				if (!box_file.empty() && !is_absolute_path(box_file))
+					box_file = std::string(pwd) + "/" + box_file;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
-		if (!lut_costs.empty() && !liberty_file.empty())
+		if ((!lut_costs.empty() || !lut_file.empty()) && !liberty_file.empty())
 			log_cmd_error("Got -lut and -liberty! This two options are exclusive.\n");
 		if (!constr_file.empty() && liberty_file.empty())
 			log_cmd_error("Got -constr but no -liberty!\n");
@@ -1373,6 +1406,9 @@ struct Abc9Pass : public Pass {
 				continue;
 			}
 
+			if (mod->attributes.count("\\abc_box_id"))
+				continue;
+
 			assign_map.set(mod);
 			signal_init.clear();
 
@@ -1395,7 +1431,8 @@ struct Abc9Pass : public Pass {
 
 			if (!dff_mode || !clk_str.empty()) {
 				abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
-						delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode);
+						delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode,
+						box_file, lut_file);
 				continue;
 			}
 
@@ -1540,7 +1577,8 @@ struct Abc9Pass : public Pass {
 				en_polarity = std::get<2>(it.first);
 				en_sig = assign_map(std::get<3>(it.first));
 				abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
-						keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode);
+						keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode,
+						box_file, lut_file);
 				assign_map.set(mod);
 			}
 		}

From e7a8955818b8b0fee02673607b429f1de0f7164e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 16:37:47 -0700
Subject: [PATCH 02/59] CIs before PIs; also sort each cell's connections
 before iterating

---
 backends/aiger/xaiger.cc | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 66ab3878e..ce93ffb28 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -215,6 +215,7 @@ struct XAigerWriter
 			RTLIL::Module* box_module = module->design->module(cell->type);
 			bool abc_box = box_module && box_module->attributes.count("\\abc_box_id");
 
+			cell->connections_.sort(RTLIL::sort_by_id_str());
 			for (const auto &c : cell->connections()) {
 				/*if (c.second.is_fully_const()) continue;*/
 				for (auto b : c.second.bits()) {
@@ -313,17 +314,17 @@ struct XAigerWriter
 		aig_map[State::S0] = 0;
 		aig_map[State::S1] = 1;
 
+		for (auto bit : input_bits) {
+			aig_m++, aig_i++;
+			aig_map[bit] = 2*aig_m;
+		}
+
 		for (auto &c : ci_bits) {
 			aig_m++, aig_i++;
 			c.second = 2*aig_m;
 			aig_map[c.first] = c.second;
 		}
 
-		for (auto bit : input_bits) {
-			aig_m++, aig_i++;
-			aig_map[bit] = 2*aig_m;
-		}
-
 		if (imode && input_bits.empty()) {
 			aig_m++, aig_i++;
 		}
@@ -585,6 +586,7 @@ struct XAigerWriter
 					holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type);
 				RTLIL::Wire *holes_wire;
 				int num_inputs = 0;
+				// NB: cell->connections_ already sorted from before
 				for (const auto &c : cell->connections()) {
 					if (cell->input(c.first)) {
 						box_inputs += c.second.size();

From ae2653c50f196a0480e715c609852218f7c57090 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 16:39:16 -0700
Subject: [PATCH 03/59] abc9 to output some more info

---
 passes/techmap/abc9.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index b14eef485..e28e3e59a 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -343,7 +343,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 	else
 		abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
 
-	abc_script += stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str());
+	abc_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
 
 	if (!script_file.empty()) {
 		if (script_file[0] == '+') {
@@ -388,6 +388,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
 
 	abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
+	abc_script += "; &ps -l -s";
 	abc_script = add_echos_to_abc_cmd(abc_script);
 
 	for (size_t i = 0; i+1 < abc_script.size(); i++)

From 7980118d74aae04479be3b9e9b59f95bf3bfbfe5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 16:39:30 -0700
Subject: [PATCH 04/59] Add ice40 box files

---
 techlibs/ice40/Makefile.inc   | 3 +++
 techlibs/ice40/cells.box      | 6 ++++++
 techlibs/ice40/cells_box.v    | 5 +++++
 techlibs/ice40/cells_sim.v    | 1 +
 techlibs/ice40/lut.lut        | 4 ++++
 techlibs/ice40/synth_ice40.cc | 9 ++++++++-
 6 files changed, 27 insertions(+), 1 deletion(-)
 create mode 100644 techlibs/ice40/cells.box
 create mode 100644 techlibs/ice40/cells_box.v
 create mode 100644 techlibs/ice40/lut.lut

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 723b59d6f..cd992bb24 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,6 +28,9 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_box.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/lut.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
new file mode 100644
index 000000000..e4cfb71e6
--- /dev/null
+++ b/techlibs/ice40/cells.box
@@ -0,0 +1,6 @@
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+126 259 231
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
new file mode 100644
index 000000000..cca88f9aa
--- /dev/null
+++ b/techlibs/ice40/cells_box.v
@@ -0,0 +1,5 @@
+(* abc_box_id = 1 *)
+module SB_CARRY (output CO, input CI, I0, I1);
+	assign CO = (I0 && I1) || ((I0 || I1) && CI);
+endmodule
+
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 62a28364b..322c1e5c7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -881,6 +881,7 @@ module SB_WARMBOOT (
 );
 endmodule
 
+(* nomem2reg *)
 module SB_SPRAM256KA (
 	input [13:0] ADDRESS,
 	input [15:0] DATAIN,
diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/lut.lut
new file mode 100644
index 000000000..48da89f46
--- /dev/null
+++ b/techlibs/ice40/lut.lut
@@ -0,0 +1,4 @@
+1	1	316
+2	1	316 379
+3	1	316 379 400
+4	1	316	379	400	449
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 6c77e5482..3faa10b4f 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -316,7 +316,14 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
 			}
 			if (!noabc) {
-				run(abc + " -dress -lut 4", "(skip if -noabc)");
+				if (abc == "abc9") {
+					run("read_verilog +/ice40/cells_box.v");
+					run("techmap -map +/techmap.v A:abc_box_id");
+					run(abc + " -dress -lut +/ice40/lut.lut -box +/ice40/cells.box", "(skip if -noabc)");
+					run("blackbox A:abc_box_id");
+				}
+				else
+					run(abc + " -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
 			if (relut || help_mode) {

From 743c164eee06abb44601e00304db18cdb36a180f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 17:34:11 -0700
Subject: [PATCH 05/59] Add SB_LUT4 to box library

---
 techlibs/ice40/cells.box   | 7 +++++++
 techlibs/ice40/cells_box.v | 7 +++++++
 techlibs/ice40/lut.lut     | 2 ++
 3 files changed, 16 insertions(+)

diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
index e4cfb71e6..d775efa78 100644
--- a/techlibs/ice40/cells.box
+++ b/techlibs/ice40/cells.box
@@ -1,6 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
+
 # NB: Inputs/Outputs must be ordered alphabetically
 
 # Inputs: CI I0 I1
 # Outputs: CO
 SB_CARRY 1 1 3 1
 126 259 231
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+316 379 400 449
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
index cca88f9aa..e2a54a42c 100644
--- a/techlibs/ice40/cells_box.v
+++ b/techlibs/ice40/cells_box.v
@@ -3,3 +3,10 @@ module SB_CARRY (output CO, input CI, I0, I1);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
+(* abc_box_id = 2 *)
+module SB_LUT4 (output O, input I0, I1, I2, I3);
+	parameter [15:0] LUT_INIT = 0;
+	// Indicate this is a black-box
+	assign O = 1'b0;
+endmodule
+
diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/lut.lut
index 48da89f46..6fa0682da 100644
--- a/techlibs/ice40/lut.lut
+++ b/techlibs/ice40/lut.lut
@@ -1,3 +1,5 @@
+# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
+
 1	1	316
 2	1	316 379
 3	1	316 379 400

From 5c134980c4d0f5c1f961d50c9c1fe1752d966e48 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 21:05:44 -0700
Subject: [PATCH 06/59] Optimise

---
 backends/aiger/xaiger.cc | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index ce93ffb28..06496dbc3 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -585,18 +585,17 @@ struct XAigerWriter
 				if (holes_module && !holes_module->cell(stringf("\\u%d", box_id)))
 					holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type);
 				RTLIL::Wire *holes_wire;
-				int num_inputs = 0;
 				// NB: cell->connections_ already sorted from before
 				for (const auto &c : cell->connections()) {
+					log_assert(c.second.size() == 1);
 					if (cell->input(c.first)) {
 						box_inputs += c.second.size();
 						if (holes_cell) {
-							holes_wire = holes_module->wire(stringf("\\i%d", num_inputs));
+							holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
 							if (!holes_wire) {
-								holes_wire = holes_module->addWire(stringf("\\i%d", num_inputs));
+								holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
 								holes_wire->port_input = true;
 							}
-							++num_inputs;
 							holes_cell->setPort(c.first, holes_wire);
 						}
 					}

From 17fb6c35229bddc636021def319547e4d8fdf271 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 08:40:50 -0700
Subject: [PATCH 07/59] Fix spacing

---
 techlibs/ice40/lut.lut | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/lut.lut
index 6fa0682da..eef997869 100644
--- a/techlibs/ice40/lut.lut
+++ b/techlibs/ice40/lut.lut
@@ -1,6 +1,6 @@
 # From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
-
-1	1	316
-2	1	316 379
-3	1	316 379 400
-4	1	316	379	400	449
+#       I3  I2  I1  I0
+1   1   316
+2   1   316 379
+3   1   316 379 400
+4   1   316 379 400 449

From e1b550d203eecacc5b79b87de7a3d49ed5713382 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 10:55:23 -0700
Subject: [PATCH 08/59] Ignore a/i/o/h XAIGER extensions

---
 frontends/aiger/aigerparse.cc | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index f2d21f1db..9c8cee63a 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -368,6 +368,13 @@ void AigerReader::parse_xaiger()
                f >> s;
                log_debug("n: '%s'\n", s.c_str());
             }
+            else if (c == 'a' || c == 'i' || c == 'o' || c == 'h') {
+                uint32_t dataSize = parse_xaiger_literal(f);
+                f.ignore(dataSize);
+            }
+            else {
+                break;
+            }
         }
         else if (c == 'i' || c == 'l' || c == 'o') {
             f.ignore(1);

From d59185f1d6bdc5f63704b41553bfc72eecd84223 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 11:08:42 -0700
Subject: [PATCH 09/59] Remove init* from xaiger, also topo-sort cells for box
 flow

---
 backends/aiger/xaiger.cc | 248 ++++++++++++++++++++++++---------------
 1 file changed, 155 insertions(+), 93 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 06496dbc3..ed0fc656f 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -20,6 +20,8 @@
 
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
+#include "kernel/celltypes.h"
+#include "kernel/utils.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -46,9 +48,8 @@ struct XAigerWriter
 	pool<SigBit> input_bits, output_bits;
 	dict<SigBit, SigBit> not_map, ff_map, alias_map;
 	dict<SigBit, pair<SigBit, SigBit>> and_map;
-	pool<SigBit> initstate_bits;
+	//pool<SigBit> initstate_bits;
 	vector<std::pair<SigBit,int>> ci_bits, co_bits;
-	dict<IdString, unsigned> type_map;
 
 	vector<pair<int, int>> aig_gates;
 	vector<int> aig_latchin, aig_latchinit, aig_outputs;
@@ -58,11 +59,11 @@ struct XAigerWriter
 	dict<SigBit, int> ordered_outputs;
 	dict<SigBit, int> ordered_latches;
 
-	dict<SigBit, int> init_inputs;
-	int initstate_ff = 0;
-
 	vector<Cell*> box_list;
 
+	//dict<SigBit, int> init_inputs;
+	//int initstate_ff = 0;
+
 	int mkgate(int a0, int a1)
 	{
 		aig_m++, aig_a++;
@@ -76,10 +77,10 @@ struct XAigerWriter
 		{
 			aig_map[bit] = -1;
 
-			if (initstate_bits.count(bit)) {
-				log_assert(initstate_ff > 0);
-				aig_map[bit] = initstate_ff;
-			} else
+			//if (initstate_bits.count(bit)) {
+			//	log_assert(initstate_ff > 0);
+			//	aig_map[bit] = initstate_ff;
+			//} else
 			if (not_map.count(bit)) {
 				int a = bit2aig(not_map.at(bit)) ^ 1;
 				aig_map[bit] = a;
@@ -170,8 +171,35 @@ struct XAigerWriter
 			if (!bit.wire->port_input)
 				unused_bits.erase(bit);
 
+		dict<SigBit, pool<IdString>> bit_drivers, bit_users;
+		TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
+		bool abc_box_seen = false;
+
 		for (auto cell : module->cells())
 		{
+			toposort.node(cell->name);
+			for (const auto &conn : cell->connections())
+			{
+				// HACK!!!
+				if (cell->type.in("\\SB_DFF", "\\SB_DFFE", "\\SB_DFFESR", "\\SB_DFFSR", "\\SB_DFFESS") && conn.first.in("\\Q"))
+					continue;
+
+				if (yosys_celltypes.cell_known(cell->type)) {
+					if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
+						continue;
+					if (cell->type == "$memrd" && conn.first == "\\DATA")
+						continue;
+				}
+
+				if (cell->input(conn.first))
+					for (auto bit : sigmap(conn.second))
+						bit_users[bit].insert(cell->name);
+
+				if (cell->output(conn.first))
+					for (auto bit : sigmap(conn.second))
+						bit_drivers[bit].insert(cell->name);
+			}
+
 			if (cell->type == "$_NOT_")
 			{
 				SigBit A = sigmap(cell->getPort("\\A").as_bit());
@@ -204,58 +232,92 @@ struct XAigerWriter
 				continue;
 			}
 
-			if (cell->type == "$initstate")
-			{
-				SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
-				undriven_bits.erase(Y);
-				initstate_bits.insert(Y);
-				continue;
-			}
+			//if (cell->type == "$initstate")
+			//{
+			//	SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
+			//	undriven_bits.erase(Y);
+			//	initstate_bits.insert(Y);
+			//	continue;
+			//}
 
 			RTLIL::Module* box_module = module->design->module(cell->type);
-			bool abc_box = box_module && box_module->attributes.count("\\abc_box_id");
-
-			cell->connections_.sort(RTLIL::sort_by_id_str());
-			for (const auto &c : cell->connections()) {
-				/*if (c.second.is_fully_const()) continue;*/
-				for (auto b : c.second.bits()) {
-					auto is_input = cell->input(c.first);
-					auto is_output = cell->output(c.first);
-					log_assert(is_input || is_output);
-					if (is_input) {
-						/*if (!w->port_input)*/ {
-							SigBit I = sigmap(b);
-							if (I != b)
-								alias_map[b] = I;
-							/*if (!output_bits.count(b))*/
-							if (abc_box)
-								co_bits.emplace_back(b, 0);
-							else if (b.wire) {
+			if (!box_module || !box_module->attributes.count("\\abc_box_id")) {
+				for (const auto &c : cell->connections()) {
+					/*if (c.second.is_fully_const()) continue;*/
+					for (auto b : c.second.bits()) {
+						Wire *w = b.wire;
+						if (!w) continue;
+						auto is_input = cell->input(c.first);
+						auto is_output = cell->output(c.first);
+						log_assert(is_input || is_output);
+						if (is_input) {
+							if (!w->port_input) {
+								SigBit I = sigmap(b);
+								if (I != b)
+									alias_map[b] = I;
 								output_bits.insert(b);
-								if (!b.wire->port_input)
-									unused_bits.erase(b);
+								unused_bits.erase(b);
 							}
 						}
-					}
-					if (is_output) {
-						SigBit O = sigmap(b);
-						/*if (!input_bits.count(O))*/
-						if (abc_box)
-							ci_bits.emplace_back(O, 0);
-						else {
+						if (is_output) {
+							SigBit O = sigmap(b);
 							input_bits.insert(O);
 							if (!O.wire->port_output)
 								undriven_bits.erase(O);
 						}
 					}
 				}
-				if (!type_map.count(cell->type))
-					type_map[cell->type] = type_map.size()+1;
+			}
+			else
+				abc_box_seen = true;
+
+			//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
+		}
+
+		if (abc_box_seen) {
+			for (auto &it : bit_users)
+				if (bit_drivers.count(it.first))
+					for (auto driver_cell : bit_drivers.at(it.first))
+					for (auto user_cell : it.second)
+						toposort.edge(driver_cell, user_cell);
+
+			toposort.sort();
+			log_assert(!toposort.found_loops);
+
+			for (auto cell_name : toposort.sorted) {
+				RTLIL::Cell *cell = module->cell(cell_name);
+				RTLIL::Module* box_module = module->design->module(cell->type);
+				if (!box_module || !box_module->attributes.count("\\abc_box_id"))
+					continue;
+
+				cell->connections_.sort(RTLIL::sort_by_id_str());
+				for (const auto &c : cell->connections()) {
+					/*if (c.second.is_fully_const()) continue;*/
+					for (auto b : c.second.bits()) {
+						auto is_input = cell->input(c.first);
+						auto is_output = cell->output(c.first);
+						log_assert(is_input || is_output);
+						if (is_input) {
+							/*if (!w->port_input)*/ {
+								SigBit I = sigmap(b);
+								if (I != b)
+									alias_map[b] = I;
+								/*if (!output_bits.count(b))*/
+									co_bits.emplace_back(b, 0);
+							}
+						}
+						if (is_output) {
+							SigBit O = sigmap(b);
+							/*if (!input_bits.count(O))*/
+								ci_bits.emplace_back(O, 0);
+						}
+					}
+				}
+
+				box_list.emplace_back(cell);
 			}
 
-			if (abc_box)
-				box_list.emplace_back(cell);
-			//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
+			// TODO: Free memory from toposort, bit_drivers, bit_users
 		}
 
 		for (auto bit : input_bits) {
@@ -329,15 +391,15 @@ struct XAigerWriter
 			aig_m++, aig_i++;
 		}
 
-		if (zinit_mode)
-		{
-			for (auto it : ff_map) {
-				if (init_map.count(it.first))
-					continue;
-				aig_m++, aig_i++;
-				init_inputs[it.first] = 2*aig_m;
-			}
-		}
+		//if (zinit_mode)
+		//{
+		//	for (auto it : ff_map) {
+		//		if (init_map.count(it.first))
+		//			continue;
+		//		aig_m++, aig_i++;
+		//		init_inputs[it.first] = 2*aig_m;
+		//	}
+		//}
 
 		for (auto it : ff_map) {
 			aig_m++, aig_l++;
@@ -349,29 +411,29 @@ struct XAigerWriter
 				aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
 		}
 
-		if (!initstate_bits.empty() || !init_inputs.empty()) {
-			aig_m++, aig_l++;
-			initstate_ff = 2*aig_m+1;
-			aig_latchinit.push_back(0);
-		}
+		//if (!initstate_bits.empty() || !init_inputs.empty()) {
+		//	aig_m++, aig_l++;
+		//	initstate_ff = 2*aig_m+1;
+		//	aig_latchinit.push_back(0);
+		//}
 
-		if (zinit_mode)
-		{
-			for (auto it : ff_map)
-			{
-				int l = ordered_latches[it.first];
+		//if (zinit_mode)
+		//{
+		//	for (auto it : ff_map)
+		//	{
+		//		int l = ordered_latches[it.first];
 
-				if (aig_latchinit.at(l) == 1)
-					aig_map[it.first] ^= 1;
+		//		if (aig_latchinit.at(l) == 1)
+		//			aig_map[it.first] ^= 1;
 
-				if (aig_latchinit.at(l) == 2)
-				{
-					int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
-					int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
-					aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
-				}
-			}
-		}
+		//		if (aig_latchinit.at(l) == 2)
+		//		{
+		//			int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
+		//			int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
+		//			aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
+		//		}
+		//	}
+		//}
 
 		for (auto it : ff_map) {
 			int a = bit2aig(it.second);
@@ -382,8 +444,8 @@ struct XAigerWriter
 				aig_latchin.push_back(a);
 		}
 
-		if (!initstate_bits.empty() || !init_inputs.empty())
-			aig_latchin.push_back(1);
+		//if (!initstate_bits.empty() || !init_inputs.empty())
+		//	aig_latchin.push_back(1);
 
 		for (auto &c : co_bits) {
 			RTLIL::SigBit bit = c.first;
@@ -518,14 +580,14 @@ struct XAigerWriter
 							symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
 					}
 
-					if (init_inputs.count(sig[i])) {
-						int a = init_inputs.at(sig[i]);
-						log_assert((a & 1) == 0);
-						if (GetSize(wire) != 1)
-							symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
-						else
-							symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
-					}
+					//if (init_inputs.count(sig[i])) {
+					//	int a = init_inputs.at(sig[i]);
+					//	log_assert((a & 1) == 0);
+					//	if (GetSize(wire) != 1)
+					//		symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
+					//	else
+					//		symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
+					//}
 
 					if (ordered_latches.count(sig[i])) {
 						int l = ordered_latches.at(sig[i]);
@@ -687,12 +749,12 @@ struct XAigerWriter
 					continue;
 				}
 
-				if (init_inputs.count(sig[i])) {
-					int a = init_inputs.at(sig[i]);
-					log_assert((a & 1) == 0);
-					init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
-					continue;
-				}
+				//if (init_inputs.count(sig[i])) {
+				//	int a = init_inputs.at(sig[i]);
+				//	log_assert((a & 1) == 0);
+				//	init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
+				//	continue;
+				//}
 
 				if (ordered_latches.count(sig[i])) {
 					int l = ordered_latches.at(sig[i]);

From a7632ab3326c5247b8152a53808413b259c13253 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 11:10:04 -0700
Subject: [PATCH 10/59] Try using an ICE40_CARRY_LUT primitive to avoid ABC
 issues

---
 techlibs/ice40/arith_map.v    | 37 +++++++++++++++++++++--------------
 techlibs/ice40/cells.box      | 12 ++++--------
 techlibs/ice40/cells_box.v    | 24 ++++++++++++++---------
 techlibs/ice40/cells_map.v    | 24 +++++++++++++++++++++++
 techlibs/ice40/cells_sim.v    | 22 +++++++++++++++++++++
 techlibs/ice40/ice40_opt.cc   | 16 +++++++++++++--
 techlibs/ice40/synth_ice40.cc |  2 +-
 7 files changed, 102 insertions(+), 35 deletions(-)

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index 4449fdc1b..eefc375dd 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,25 +44,32 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-		SB_CARRY carry (
-			.I0(AA[i]),
-			.I1(BB[i]),
-			.CI(C[i]),
-			.CO(CO[i])
-		);
-		SB_LUT4 #(
-			//         I0: 1010 1010 1010 1010
-			//         I1: 1100 1100 1100 1100
-			//         I2: 1111 0000 1111 0000
-			//         I3: 1111 1111 0000 0000
-			.LUT_INIT(16'b 0110_1001_1001_0110)
-		) adder (
-			.I0(1'b0),
+		ICE40_CARRY_LUT carry_lut (
 			.I1(AA[i]),
 			.I2(BB[i]),
-			.I3(C[i]),
+			.CI(C[i]),
+			.CO(CO[i]),
 			.O(Y[i])
 		);
+//		SB_CARRY carry (
+//			.I0(AA[i]),
+//			.I1(BB[i]),
+//			.CI(C[i]),
+//			.CO(CO[i])
+//		);
+//		SB_LUT4 #(
+//			//         I0: 1010 1010 1010 1010
+//			//         I1: 1100 1100 1100 1100
+//			//         I2: 1111 0000 1111 0000
+//			//         I3: 1111 1111 0000 0000
+//			.LUT_INIT(16'b 0110_1001_1001_0110)
+//		) adder (
+//			.I0(1'b0),
+//			.I1(AA[i]),
+//			.I2(BB[i]),
+//			.I3(C[i]),
+//			.O(Y[i])
+//		);
 	end endgenerate
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
index d775efa78..34d1f372e 100644
--- a/techlibs/ice40/cells.box
+++ b/techlibs/ice40/cells.box
@@ -2,12 +2,8 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
-# Inputs: CI I0 I1
-# Outputs: CO
-SB_CARRY 1 1 3 1
+# Inputs: CI I1 I2
+# Outputs: CO O
+ICE40_CARRY_LUT 1 1 3 2
 126 259 231
-
-# Inputs: I0 I1 I2 I3
-# Outputs: O
-SB_LUT4 2 1 4 1
-316 379 400 449
+316 400 379
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
index e2a54a42c..d0eb8708c 100644
--- a/techlibs/ice40/cells_box.v
+++ b/techlibs/ice40/cells_box.v
@@ -1,12 +1,18 @@
 (* abc_box_id = 1 *)
-module SB_CARRY (output CO, input CI, I0, I1);
-	assign CO = (I0 && I1) || ((I0 || I1) && CI);
-endmodule
+module ICE40_CARRY_LUT (output CO, O, input CI, I1, I2);
+	assign CO = (I1 && I2) || ((I1 || I2) && CI);
 
-(* abc_box_id = 2 *)
-module SB_LUT4 (output O, input I0, I1, I2, I3);
-	parameter [15:0] LUT_INIT = 0;
-	// Indicate this is a black-box
-	assign O = 1'b0;
-endmodule
+	wire I0, I3;
+	assign I0 = 1'b0;
+	assign I3 = CI;
 
+	//                            I0: 1010 1010 1010 1010
+	//                            I1: 1100 1100 1100 1100
+	//                            I2: 1111 0000 1111 0000
+	//                            I3: 1111 1111 0000 0000
+	localparam [15:0] LUT_INIT = 16'b 0110_1001_1001_0110;
+	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
+	wire [3:0] s2 = I2 ?       s3[ 7:4] :       s3[3:0];
+	wire [1:0] s1 = I1 ?       s2[ 3:2] :       s2[1:0];
+	assign O = I0 ? s1[1] : s1[0];
+endmodule
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index d0ddfd02e..d4c611686 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -57,3 +57,27 @@ module \$lut (A, Y);
   endgenerate
 endmodule
 `endif
+
+`ifndef NO_CARRY
+module ICE40_CARRY_LUT (output CO, O, input CI, I1, I2);
+	SB_CARRY carry (
+		.I0(I1),
+		.I1(I2),
+		.CI(CI),
+		.CO(CO),
+	);
+	SB_LUT4 #(
+		//         I0: 1010 1010 1010 1010
+		//         I1: 1100 1100 1100 1100
+		//         I2: 1111 0000 1111 0000
+		//         I3: 1111 1111 0000 0000
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(I1),
+		.I2(I2),
+		.I3(CI),
+		.O(O)
+	);
+endmodule
+`endif
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 322c1e5c7..b5a739a63 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1384,3 +1384,25 @@ module SB_MAC16 (
 	assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
 	assign O = {Oh, Ol};
 endmodule
+
+module ICE40_CARRY_LUT (input CI, input I1, input I2, output CO, output O);
+	SB_CARRY carry (
+		.I0(I1),
+		.I1(I2),
+		.CI(CI),
+		.CO(CO),
+	);
+	SB_LUT4 #(
+		//         I0: 1010 1010 1010 1010
+		//         I1: 1100 1100 1100 1100
+		//         I2: 1111 0000 1111 0000
+		//         I3: 1111 1111 0000 0000
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(I1),
+		.I2(I2),
+		.I3(CI),
+		.O(O)
+	);
+endmodule
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index f528607d6..edb293b93 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -47,16 +47,20 @@ static void run_ice40_opts(Module *module)
 			continue;
 		}
 
-		if (cell->type == "\\SB_CARRY")
+		if (cell->type.in("\\SB_CARRY", "\\ICE40_CARRY_LUT"))
 		{
 			SigSpec non_const_inputs, replacement_output;
 			int count_zeros = 0, count_ones = 0;
 
 			SigBit inbit[3] = {
-				get_bit_or_zero(cell->getPort("\\I0")),
 				get_bit_or_zero(cell->getPort("\\I1")),
 				get_bit_or_zero(cell->getPort("\\CI"))
 			};
+			if (cell->type == "\\SB_CARRY")
+				inbit[2] = get_bit_or_zero(cell->getPort("\\I0"));
+			else if (cell->type == "\\ICE40_CARRY_LUT")
+				inbit[2] = get_bit_or_zero(cell->getPort("\\I2"));
+			else log_abort();
 			for (int i = 0; i < 3; i++)
 				if (inbit[i].wire == nullptr) {
 					if (inbit[i] == State::S1)
@@ -79,6 +83,14 @@ static void run_ice40_opts(Module *module)
 				module->design->scratchpad_set_bool("opt.did_something", true);
 				log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
+
+				if (cell->type == "\\ICE40_CARRY_LUT")
+					module->addLut(NEW_ID,
+						{ RTLIL::S0, cell->getPort("\\I1"), cell->getPort("\\I2"), cell->getPort("\\CI") },
+						cell->getPort("\\O"),
+						RTLIL::Const("0110_1001_1001_0110"),
+						cell->get_src_attribute());
+
 				module->remove(cell);
 			}
 			continue;
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 3faa10b4f..d09a1184c 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -296,7 +296,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("opt_merge");
 				run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
 			}
-			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
+			run("techmap -D NO_LUT -D NO_CARRY -map +/ice40/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 			run("ice40_ffinit");

From c1ebe51a75ef8ce47d6b1406fa87b15bd8f97760 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 11:10:20 -0700
Subject: [PATCH 11/59] Revert "Try using an ICE40_CARRY_LUT primitive to avoid
 ABC issues"

This reverts commit a7632ab3326c5247b8152a53808413b259c13253.
---
 techlibs/ice40/arith_map.v    | 37 ++++++++++++++---------------------
 techlibs/ice40/cells.box      | 12 ++++++++----
 techlibs/ice40/cells_box.v    | 26 ++++++++++--------------
 techlibs/ice40/cells_map.v    | 24 -----------------------
 techlibs/ice40/cells_sim.v    | 22 ---------------------
 techlibs/ice40/ice40_opt.cc   | 16 ++-------------
 techlibs/ice40/synth_ice40.cc |  2 +-
 7 files changed, 36 insertions(+), 103 deletions(-)

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index eefc375dd..4449fdc1b 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -44,32 +44,25 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-		ICE40_CARRY_LUT carry_lut (
+		SB_CARRY carry (
+			.I0(AA[i]),
+			.I1(BB[i]),
+			.CI(C[i]),
+			.CO(CO[i])
+		);
+		SB_LUT4 #(
+			//         I0: 1010 1010 1010 1010
+			//         I1: 1100 1100 1100 1100
+			//         I2: 1111 0000 1111 0000
+			//         I3: 1111 1111 0000 0000
+			.LUT_INIT(16'b 0110_1001_1001_0110)
+		) adder (
+			.I0(1'b0),
 			.I1(AA[i]),
 			.I2(BB[i]),
-			.CI(C[i]),
-			.CO(CO[i]),
+			.I3(C[i]),
 			.O(Y[i])
 		);
-//		SB_CARRY carry (
-//			.I0(AA[i]),
-//			.I1(BB[i]),
-//			.CI(C[i]),
-//			.CO(CO[i])
-//		);
-//		SB_LUT4 #(
-//			//         I0: 1010 1010 1010 1010
-//			//         I1: 1100 1100 1100 1100
-//			//         I2: 1111 0000 1111 0000
-//			//         I3: 1111 1111 0000 0000
-//			.LUT_INIT(16'b 0110_1001_1001_0110)
-//		) adder (
-//			.I0(1'b0),
-//			.I1(AA[i]),
-//			.I2(BB[i]),
-//			.I3(C[i]),
-//			.O(Y[i])
-//		);
 	end endgenerate
 
 	assign X = AA ^ BB;
diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/cells.box
index 34d1f372e..d775efa78 100644
--- a/techlibs/ice40/cells.box
+++ b/techlibs/ice40/cells.box
@@ -2,8 +2,12 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
-# Inputs: CI I1 I2
-# Outputs: CO O
-ICE40_CARRY_LUT 1 1 3 2
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
 126 259 231
-316 400 379
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+316 379 400 449
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/cells_box.v
index d0eb8708c..e2a54a42c 100644
--- a/techlibs/ice40/cells_box.v
+++ b/techlibs/ice40/cells_box.v
@@ -1,18 +1,12 @@
 (* abc_box_id = 1 *)
-module ICE40_CARRY_LUT (output CO, O, input CI, I1, I2);
-	assign CO = (I1 && I2) || ((I1 || I2) && CI);
-
-	wire I0, I3;
-	assign I0 = 1'b0;
-	assign I3 = CI;
-
-	//                            I0: 1010 1010 1010 1010
-	//                            I1: 1100 1100 1100 1100
-	//                            I2: 1111 0000 1111 0000
-	//                            I3: 1111 1111 0000 0000
-	localparam [15:0] LUT_INIT = 16'b 0110_1001_1001_0110;
-	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
-	wire [3:0] s2 = I2 ?       s3[ 7:4] :       s3[3:0];
-	wire [1:0] s1 = I1 ?       s2[ 3:2] :       s2[1:0];
-	assign O = I0 ? s1[1] : s1[0];
+module SB_CARRY (output CO, input CI, I0, I1);
+	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
+
+(* abc_box_id = 2 *)
+module SB_LUT4 (output O, input I0, I1, I2, I3);
+	parameter [15:0] LUT_INIT = 0;
+	// Indicate this is a black-box
+	assign O = 1'b0;
+endmodule
+
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index d4c611686..d0ddfd02e 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -57,27 +57,3 @@ module \$lut (A, Y);
   endgenerate
 endmodule
 `endif
-
-`ifndef NO_CARRY
-module ICE40_CARRY_LUT (output CO, O, input CI, I1, I2);
-	SB_CARRY carry (
-		.I0(I1),
-		.I1(I2),
-		.CI(CI),
-		.CO(CO),
-	);
-	SB_LUT4 #(
-		//         I0: 1010 1010 1010 1010
-		//         I1: 1100 1100 1100 1100
-		//         I2: 1111 0000 1111 0000
-		//         I3: 1111 1111 0000 0000
-		.LUT_INIT(16'b 0110_1001_1001_0110)
-	) adder (
-		.I0(1'b0),
-		.I1(I1),
-		.I2(I2),
-		.I3(CI),
-		.O(O)
-	);
-endmodule
-`endif
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b5a739a63..322c1e5c7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1384,25 +1384,3 @@ module SB_MAC16 (
 	assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
 	assign O = {Oh, Ol};
 endmodule
-
-module ICE40_CARRY_LUT (input CI, input I1, input I2, output CO, output O);
-	SB_CARRY carry (
-		.I0(I1),
-		.I1(I2),
-		.CI(CI),
-		.CO(CO),
-	);
-	SB_LUT4 #(
-		//         I0: 1010 1010 1010 1010
-		//         I1: 1100 1100 1100 1100
-		//         I2: 1111 0000 1111 0000
-		//         I3: 1111 1111 0000 0000
-		.LUT_INIT(16'b 0110_1001_1001_0110)
-	) adder (
-		.I0(1'b0),
-		.I1(I1),
-		.I2(I2),
-		.I3(CI),
-		.O(O)
-	);
-endmodule
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index edb293b93..f528607d6 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -47,20 +47,16 @@ static void run_ice40_opts(Module *module)
 			continue;
 		}
 
-		if (cell->type.in("\\SB_CARRY", "\\ICE40_CARRY_LUT"))
+		if (cell->type == "\\SB_CARRY")
 		{
 			SigSpec non_const_inputs, replacement_output;
 			int count_zeros = 0, count_ones = 0;
 
 			SigBit inbit[3] = {
+				get_bit_or_zero(cell->getPort("\\I0")),
 				get_bit_or_zero(cell->getPort("\\I1")),
 				get_bit_or_zero(cell->getPort("\\CI"))
 			};
-			if (cell->type == "\\SB_CARRY")
-				inbit[2] = get_bit_or_zero(cell->getPort("\\I0"));
-			else if (cell->type == "\\ICE40_CARRY_LUT")
-				inbit[2] = get_bit_or_zero(cell->getPort("\\I2"));
-			else log_abort();
 			for (int i = 0; i < 3; i++)
 				if (inbit[i].wire == nullptr) {
 					if (inbit[i] == State::S1)
@@ -83,14 +79,6 @@ static void run_ice40_opts(Module *module)
 				module->design->scratchpad_set_bool("opt.did_something", true);
 				log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
 						log_id(module), log_id(cell), log_signal(replacement_output));
-
-				if (cell->type == "\\ICE40_CARRY_LUT")
-					module->addLut(NEW_ID,
-						{ RTLIL::S0, cell->getPort("\\I1"), cell->getPort("\\I2"), cell->getPort("\\CI") },
-						cell->getPort("\\O"),
-						RTLIL::Const("0110_1001_1001_0110"),
-						cell->get_src_attribute());
-
 				module->remove(cell);
 			}
 			continue;
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index d09a1184c..3faa10b4f 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -296,7 +296,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("opt_merge");
 				run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
 			}
-			run("techmap -D NO_LUT -D NO_CARRY -map +/ice40/cells_map.v");
+			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 			run("ice40_ffinit");

From 42c33db22caeffa05bde59d915a4433b756929a1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 12:15:34 -0700
Subject: [PATCH 12/59] Rename to abc.*

---
 techlibs/ice40/{cells.box => abc.box} | 0
 techlibs/ice40/{lut.lut => abc.lut}   | 0
 techlibs/ice40/{cells_box.v => abc.v} | 0
 3 files changed, 0 insertions(+), 0 deletions(-)
 rename techlibs/ice40/{cells.box => abc.box} (100%)
 rename techlibs/ice40/{lut.lut => abc.lut} (100%)
 rename techlibs/ice40/{cells_box.v => abc.v} (100%)

diff --git a/techlibs/ice40/cells.box b/techlibs/ice40/abc.box
similarity index 100%
rename from techlibs/ice40/cells.box
rename to techlibs/ice40/abc.box
diff --git a/techlibs/ice40/lut.lut b/techlibs/ice40/abc.lut
similarity index 100%
rename from techlibs/ice40/lut.lut
rename to techlibs/ice40/abc.lut
diff --git a/techlibs/ice40/cells_box.v b/techlibs/ice40/abc.v
similarity index 100%
rename from techlibs/ice40/cells_box.v
rename to techlibs/ice40/abc.v

From 4fb9ccfcd81db6d2e574bea3d142b714126d1123 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 12:22:03 -0700
Subject: [PATCH 13/59] synth_ice40 to use renamed files

---
 techlibs/ice40/synth_ice40.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 3faa10b4f..91cd063a2 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -317,9 +317,9 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			if (!noabc) {
 				if (abc == "abc9") {
-					run("read_verilog +/ice40/cells_box.v");
+					run("read_verilog +/ice40/abc.v");
 					run("techmap -map +/techmap.v A:abc_box_id");
-					run(abc + " -dress -lut +/ice40/lut.lut -box +/ice40/cells.box", "(skip if -noabc)");
+					run(abc + " -dress -lut +/ice40/abc.lut -box +/ice40/abc.box", "(skip if -noabc)");
 					run("blackbox A:abc_box_id");
 				}
 				else

From 1eade0667102b50afa927f64e22968dd28365167 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 12:27:02 -0700
Subject: [PATCH 14/59] Also update Makefile.inc

---
 techlibs/ice40/Makefile.inc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index cd992bb24..abfede011 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,9 +28,9 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_box.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/lut.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))

From 58847df1b94d2caaa1fe959acb04425397f3567f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 12:27:45 -0700
Subject: [PATCH 15/59] Mark seq output ports with "abc_flop_q" attr

---
 techlibs/ice40/cells_sim.v | 48 +++++++++++++++++++-------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 322c1e5c7..cf7b9d252 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -132,18 +132,18 @@ endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF (output `SB_DFF_REG, input C, D);
+module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
 	always @(posedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -151,7 +151,7 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -159,7 +159,7 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -167,7 +167,7 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -175,7 +175,7 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -185,7 +185,7 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -193,7 +193,7 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -203,7 +203,7 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -213,18 +213,18 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN (output `SB_DFF_REG, input C, D);
+module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -232,7 +232,7 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -240,7 +240,7 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -248,7 +248,7 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -256,7 +256,7 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -266,7 +266,7 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -274,7 +274,7 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -284,7 +284,7 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -295,7 +295,7 @@ endmodule
 // SiliconBlue RAM Cells
 
 module SB_RAM40_4K (
-	output [15:0] RDATA,
+	(* abc_flop_q *) output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLK, WCLKE, WE,
@@ -463,7 +463,7 @@ module SB_RAM40_4K (
 endmodule
 
 module SB_RAM40_4KNR (
-	output [15:0] RDATA,
+	(* abc_flop_q *) output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLK, WCLKE, WE,
@@ -528,7 +528,7 @@ module SB_RAM40_4KNR (
 endmodule
 
 module SB_RAM40_4KNW (
-	output [15:0] RDATA,
+	(* abc_flop_q *) output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLKN, WCLKE, WE,
@@ -593,7 +593,7 @@ module SB_RAM40_4KNW (
 endmodule
 
 module SB_RAM40_4KNRNW (
-	output [15:0] RDATA,
+	(* abc_flop_q *) output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
 	input         WCLKN, WCLKE, WE,

From 2b860809e9dae557a435f01a3125e6dd4b4a8599 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 12:28:19 -0700
Subject: [PATCH 16/59] Stop topological sort at abc_flop_q

---
 backends/aiger/xaiger.cc | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index ed0fc656f..070d6d403 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -180,14 +180,20 @@ struct XAigerWriter
 			toposort.node(cell->name);
 			for (const auto &conn : cell->connections())
 			{
-				// HACK!!!
-				if (cell->type.in("\\SB_DFF", "\\SB_DFFE", "\\SB_DFFESR", "\\SB_DFFSR", "\\SB_DFFESS") && conn.first.in("\\Q"))
-					continue;
+				if (!cell->type.in("$_NOT_", "$_AND_")) {
+					if (yosys_celltypes.cell_known(cell->type)) {
+						if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
+							continue;
+						if (cell->type == "$memrd" && conn.first == "\\DATA")
+							continue;
+					}
 
-				if (yosys_celltypes.cell_known(cell->type)) {
-					if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
-						continue;
-					if (cell->type == "$memrd" && conn.first == "\\DATA")
+					RTLIL::Module* inst_module = module->design->module(cell->type);
+					log_assert(inst_module);
+					RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
+					log_assert(inst_module_port);
+
+					if (inst_module_port->attributes.count("\\abc_flop_q"))
 						continue;
 				}
 

From fd89c1056ef8a8010c77a5b645df14908e3c68d9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 12:33:32 -0700
Subject: [PATCH 17/59] Working ABC9 script

---
 passes/techmap/abc9.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index e28e3e59a..429bdb293 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -25,7 +25,8 @@
 #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
 #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
 //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2"
-#define ABC_COMMAND_LUT "&st; &fraig; &scorr; &dc2; &retime; &dch -f; &if; &mfs"
+//#define ABC_COMMAND_LUT "&st; &sweep; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps"
+#define ABC_COMMAND_LUT "&st; &scorr; &dc2; &retime; &dch -f; &if; &ps -l -m -s"
 #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}"
 #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
 
@@ -388,7 +389,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
 
 	abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
-	abc_script += "; &ps -l -s";
 	abc_script = add_echos_to_abc_cmd(abc_script);
 
 	for (size_t i = 0; i+1 < abc_script.size(); i++)

From 437fec0d88b4a2ad172edf0d1a861a38845f3b1d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 13:01:17 -0700
Subject: [PATCH 18/59] Map to SB_LUT4 from fastest input first

---
 techlibs/ice40/cells_map.v | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index d0ddfd02e..287c48b11 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -37,20 +37,24 @@ module \$lut (A, Y);
 
   generate
     if (WIDTH == 1) begin
-      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
+      localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
+      SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(1'b0), .I1(1'b0), .I2(1'b0), .I3(A[0]));
     end else
     if (WIDTH == 2) begin
-      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
+      localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[1]}}, {4{LUT[2]}}, {4{LUT[0]}}};
+      SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(1'b0), .I1(1'b0), .I2(A[1]), .I3(A[0]));
     end else
     if (WIDTH == 3) begin
-      SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
+      localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[3]}}, {2{LUT[5]}}, {2{LUT[1]}}, {2{LUT[6]}}, {2{LUT[2]}}, {2{LUT[4]}}, {2{LUT[0]}}};
+      SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(1'b0), .I1(A[2]), .I2(A[1]), .I3(A[0]));
     end else
     if (WIDTH == 4) begin
+      localparam [15:0] INIT = {LUT[15], LUT[7], LUT[11], LUT[3], LUT[13], LUT[5], LUT[9], LUT[1], LUT[14], LUT[6], LUT[10], LUT[2], LUT[12], LUT[4], LUT[8], LUT[0]};
       SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
+        .I0(A[3]), .I1(A[2]), .I2(A[1]), .I3(A[0]));
     end else begin
       wire _TECHMAP_FAIL_ = 1;
     end

From 1ec5f18346dd3f50e2340f4b79239a045ce7dd72 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 14:43:45 -0700
Subject: [PATCH 19/59] Cope with inout ports

---
 backends/aiger/xaiger.cc | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 070d6d403..14fa4fb7f 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -197,9 +197,12 @@ struct XAigerWriter
 						continue;
 				}
 
-				if (cell->input(conn.first))
+				if (cell->input(conn.first)) {
+					// Ignore inout for the sake of topographical ordering
+					if (cell->output(conn.first)) continue;
 					for (auto bit : sigmap(conn.second))
 						bit_users[bit].insert(cell->name);
+				}
 
 				if (cell->output(conn.first))
 					for (auto bit : sigmap(conn.second))
@@ -287,7 +290,18 @@ struct XAigerWriter
 					for (auto user_cell : it.second)
 						toposort.edge(driver_cell, user_cell);
 
+#ifndef NDEBUG
+			toposort.analyze_loops = true;
+#endif
 			toposort.sort();
+#ifndef NDEBUG
+			for (auto &it : toposort.loops) {
+				log("  loop");
+				for (auto cell : it)
+					log(" %s", log_id(cell));
+				log("\n");
+			}
+#endif
 			log_assert(!toposort.found_loops);
 
 			for (auto cell_name : toposort.sorted) {

From 671cca59a9f63f9fb7102727eb4dee1b18fe3ef6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 14:44:08 -0700
Subject: [PATCH 20/59] Missing abc_flop_q attribute on SPRAM

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index cf7b9d252..70cd51ed1 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -887,7 +887,7 @@ module SB_SPRAM256KA (
 	input [15:0] DATAIN,
 	input [3:0] MASKWREN,
 	input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
-	output reg [15:0] DATAOUT
+	(* abc_flop_q *) output reg [15:0] DATAOUT
 );
 `ifndef BLACKBOX
 `ifndef EQUIV

From 6f3e5297dbf1a0b28e6bfa51990f957939d722d7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:04:46 -0700
Subject: [PATCH 21/59] Add "-device" argument to synth_ice40

---
 techlibs/ice40/Makefile.inc          |  6 ++++--
 techlibs/ice40/{abc.box => hx8k.box} |  4 ++--
 techlibs/ice40/{abc.lut => hx8k.lut} |  2 +-
 techlibs/ice40/synth_ice40.cc        | 15 +++++++++++++--
 4 files changed, 20 insertions(+), 7 deletions(-)
 rename techlibs/ice40/{abc.box => hx8k.box} (70%)
 rename techlibs/ice40/{abc.lut => hx8k.lut} (64%)

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index abfede011..efcea6e98 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,9 +28,11 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.box))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
diff --git a/techlibs/ice40/abc.box b/techlibs/ice40/hx8k.box
similarity index 70%
rename from techlibs/ice40/abc.box
rename to techlibs/ice40/hx8k.box
index d775efa78..c31f7bf39 100644
--- a/techlibs/ice40/abc.box
+++ b/techlibs/ice40/hx8k.box
@@ -1,4 +1,4 @@
-# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
@@ -10,4 +10,4 @@ SB_CARRY 1 1 3 1
 # Inputs: I0 I1 I2 I3
 # Outputs: O
 SB_LUT4 2 1 4 1
-316 379 400 449
+449 400 379 316
diff --git a/techlibs/ice40/abc.lut b/techlibs/ice40/hx8k.lut
similarity index 64%
rename from techlibs/ice40/abc.lut
rename to techlibs/ice40/hx8k.lut
index eef997869..3b3bb11e2 100644
--- a/techlibs/ice40/abc.lut
+++ b/techlibs/ice40/hx8k.lut
@@ -1,4 +1,4 @@
-# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
 #       I3  I2  I1  I0
 1   1   316
 2   1   316 379
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 91cd063a2..2981875eb 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -37,6 +37,10 @@ struct SynthIce40Pass : public ScriptPass
 		log("\n");
 		log("This command runs synthesis for iCE40 FPGAs.\n");
 		log("\n");
+		log("    -device < hx1k | lp384 | lp1k | lp8k | hx8k | u4k | up5k >\n");
+		log("        optimise the synthesis netlist for the specified device.\n");
+		log("        HX1K is the default target if no device argument specified.\n");
+		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
 		log("\n");
@@ -102,7 +106,7 @@ struct SynthIce40Pass : public ScriptPass
 	}
 
 
-	string top_opt, blif_file, edif_file, json_file, abc;
+	string top_opt, blif_file, edif_file, json_file, abc, device_opt;
 	bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
 	int min_ce_use;
 
@@ -124,6 +128,7 @@ struct SynthIce40Pass : public ScriptPass
 		abc2 = false;
 		vpr = false;
 		abc = "abc";
+		device_opt = "hx1k";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -210,12 +215,18 @@ struct SynthIce40Pass : public ScriptPass
 				abc = "abc9";
 				continue;
 			}
+			if (args[argidx] == "-device" && argidx+1 < args.size()) {
+				device_opt = args[++argidx];
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
+		if (device_opt != "hx1k" && device_opt !="lp384" && device_opt != "lp1k" && device_opt !="lp8k" && device_opt !="hx8k" && device_opt != "u4k" && device_opt != "up5k")
+			log_cmd_error("Invalid or no family specified: '%s'\n", device_opt.c_str());
 
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();
@@ -319,7 +330,7 @@ struct SynthIce40Pass : public ScriptPass
 				if (abc == "abc9") {
 					run("read_verilog +/ice40/abc.v");
 					run("techmap -map +/techmap.v A:abc_box_id");
-					run(abc + " -dress -lut +/ice40/abc.lut -box +/ice40/abc.box", "(skip if -noabc)");
+					run(abc + stringf(" -dress -lut +/ice40/%s.lut -box +/ice40/%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
 					run("blackbox A:abc_box_id");
 				}
 				else

From 3105a8a6531545efefe228fb4fc4b7b09ae127e8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:07:44 -0700
Subject: [PATCH 22/59] Update error message

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2981875eb..62589ad87 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -226,7 +226,7 @@ struct SynthIce40Pass : public ScriptPass
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
 		if (device_opt != "hx1k" && device_opt !="lp384" && device_opt != "lp1k" && device_opt !="lp8k" && device_opt !="hx8k" && device_opt != "u4k" && device_opt != "up5k")
-			log_cmd_error("Invalid or no family specified: '%s'\n", device_opt.c_str());
+			log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
 
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();

From 4b520ae627f696499eb91b1b4e762ef0b1dfdd2d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:10:22 -0700
Subject: [PATCH 23/59] Fix grammar

---
 techlibs/intel/synth_intel.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 0f1d7a7b5..d2291b8d4 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -38,7 +38,7 @@ struct SynthIntelPass : public ScriptPass {
     log("\n");
     log("    -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
     log("        generate the synthesis netlist for the specified family.\n");
-    log("        MAX10 is the default target if not family argument specified.\n");
+    log("        MAX10 is the default target if no family argument specified.\n");
     log("        For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
     log("        Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n");
     log("\n");
@@ -146,7 +146,7 @@ struct SynthIntelPass : public ScriptPass {
     if (!design->full_selection())
       log_cmd_error("This command only operates on fully selected designs!\n");
     if (family_opt != "max10" && family_opt !="a10gx" && family_opt != "cyclonev" && family_opt !="cycloneiv" && family_opt !="cycloneive" && family_opt != "cyclone10")
-      log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
+      log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str());
 
     log_header(design, "Executing SYNTH_INTEL pass.\n");
     log_push();

From 5c0853fc518bbbad77b819a5c916e438d0e33cb0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:10:39 -0700
Subject: [PATCH 24/59] Add up5k timings

---
 techlibs/ice40/up5k.box | 13 +++++++++++++
 techlibs/ice40/up5k.lut |  6 ++++++
 2 files changed, 19 insertions(+)
 create mode 100644 techlibs/ice40/up5k.box
 create mode 100644 techlibs/ice40/up5k.lut

diff --git a/techlibs/ice40/up5k.box b/techlibs/ice40/up5k.box
new file mode 100644
index 000000000..94df1df8f
--- /dev/null
+++ b/techlibs/ice40/up5k.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+278 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+1285 1231 1205 874
diff --git a/techlibs/ice40/up5k.lut b/techlibs/ice40/up5k.lut
new file mode 100644
index 000000000..1e4fcadb6
--- /dev/null
+++ b/techlibs/ice40/up5k.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+#       I3  I2  I1  I0
+1   1   874
+2   1   874 1205
+3   1   874 1205 1231
+4   1   874 1205 1231 1285

From abcd3103ffa8965160e2d489c81e0a61c9a937bd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:11:14 -0700
Subject: [PATCH 25/59] Do not print slack histogram

---
 passes/techmap/abc9.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 429bdb293..8b5b172ab 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -26,7 +26,7 @@
 #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
 //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2"
 //#define ABC_COMMAND_LUT "&st; &sweep; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps"
-#define ABC_COMMAND_LUT "&st; &scorr; &dc2; &retime; &dch -f; &if; &ps -l -m -s"
+#define ABC_COMMAND_LUT "&st; &scorr; &dc2; &retime; &dch -f; &if; &ps -l -m"
 #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}"
 #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
 

From c795e14d25b42ae28bd4b8f7e259e969442437b3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:19:02 -0700
Subject: [PATCH 26/59] Reduce to three devices: hx, lp, u

---
 techlibs/ice40/{hx8k.box => hx.box} |  0
 techlibs/ice40/{hx8k.lut => hx.lut} |  0
 techlibs/ice40/lp.box               | 13 +++++++++++++
 techlibs/ice40/lp.lut               |  6 ++++++
 techlibs/ice40/synth_ice40.cc       |  8 ++++----
 techlibs/ice40/{up5k.box => u.box}  |  0
 techlibs/ice40/{up5k.lut => u.lut}  |  0
 7 files changed, 23 insertions(+), 4 deletions(-)
 rename techlibs/ice40/{hx8k.box => hx.box} (100%)
 rename techlibs/ice40/{hx8k.lut => hx.lut} (100%)
 create mode 100644 techlibs/ice40/lp.box
 create mode 100644 techlibs/ice40/lp.lut
 rename techlibs/ice40/{up5k.box => u.box} (100%)
 rename techlibs/ice40/{up5k.lut => u.lut} (100%)

diff --git a/techlibs/ice40/hx8k.box b/techlibs/ice40/hx.box
similarity index 100%
rename from techlibs/ice40/hx8k.box
rename to techlibs/ice40/hx.box
diff --git a/techlibs/ice40/hx8k.lut b/techlibs/ice40/hx.lut
similarity index 100%
rename from techlibs/ice40/hx8k.lut
rename to techlibs/ice40/hx.lut
diff --git a/techlibs/ice40/lp.box b/techlibs/ice40/lp.box
new file mode 100644
index 000000000..7eb8e86e0
--- /dev/null
+++ b/techlibs/ice40/lp.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+186 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+465 558 589 661
diff --git a/techlibs/ice40/lp.lut b/techlibs/ice40/lp.lut
new file mode 100644
index 000000000..e72f760a2
--- /dev/null
+++ b/techlibs/ice40/lp.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
+#       I3  I2  I1  I0
+1   1   465
+2   1   465 558
+3   1   465 558 589
+4   1   465 558 589 661
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 62589ad87..7c95588e4 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -37,9 +37,9 @@ struct SynthIce40Pass : public ScriptPass
 		log("\n");
 		log("This command runs synthesis for iCE40 FPGAs.\n");
 		log("\n");
-		log("    -device < hx1k | lp384 | lp1k | lp8k | hx8k | u4k | up5k >\n");
+		log("    -device < hx | lp | u >\n");
 		log("        optimise the synthesis netlist for the specified device.\n");
-		log("        HX1K is the default target if no device argument specified.\n");
+		log("        HX is the default target if no device argument specified.\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
@@ -128,7 +128,7 @@ struct SynthIce40Pass : public ScriptPass
 		abc2 = false;
 		vpr = false;
 		abc = "abc";
-		device_opt = "hx1k";
+		device_opt = "hx";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -225,7 +225,7 @@ struct SynthIce40Pass : public ScriptPass
 
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
-		if (device_opt != "hx1k" && device_opt !="lp384" && device_opt != "lp1k" && device_opt !="lp8k" && device_opt !="hx8k" && device_opt != "u4k" && device_opt != "up5k")
+		if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
 			log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
 
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
diff --git a/techlibs/ice40/up5k.box b/techlibs/ice40/u.box
similarity index 100%
rename from techlibs/ice40/up5k.box
rename to techlibs/ice40/u.box
diff --git a/techlibs/ice40/up5k.lut b/techlibs/ice40/u.lut
similarity index 100%
rename from techlibs/ice40/up5k.lut
rename to techlibs/ice40/u.lut

From 8fd455c91070e1e4cf05cbece79999fef04bb9b9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 15:19:48 -0700
Subject: [PATCH 27/59] Update Makefile.inc too

---
 techlibs/ice40/Makefile.inc | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index efcea6e98..cb2121a11 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -29,10 +29,12 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/lp.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/lp.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/u.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/u.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))

From 23cd2e5de042949bf47a9c72b8dd8fae48e900ce Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 16:03:29 -0700
Subject: [PATCH 28/59] Fix $anyseq warning and cleanup

---
 backends/aiger/xaiger.cc | 23 +++++++----------------
 1 file changed, 7 insertions(+), 16 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 14fa4fb7f..582c49976 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -252,7 +252,7 @@ struct XAigerWriter
 			RTLIL::Module* box_module = module->design->module(cell->type);
 			if (!box_module || !box_module->attributes.count("\\abc_box_id")) {
 				for (const auto &c : cell->connections()) {
-					/*if (c.second.is_fully_const()) continue;*/
+					if (c.second.is_fully_const()) continue;
 					for (auto b : c.second.bits()) {
 						Wire *w = b.wire;
 						if (!w) continue;
@@ -271,8 +271,7 @@ struct XAigerWriter
 						if (is_output) {
 							SigBit O = sigmap(b);
 							input_bits.insert(O);
-							if (!O.wire->port_output)
-								undriven_bits.erase(O);
+							undriven_bits.erase(O);
 						}
 					}
 				}
@@ -312,24 +311,19 @@ struct XAigerWriter
 
 				cell->connections_.sort(RTLIL::sort_by_id_str());
 				for (const auto &c : cell->connections()) {
-					/*if (c.second.is_fully_const()) continue;*/
 					for (auto b : c.second.bits()) {
 						auto is_input = cell->input(c.first);
 						auto is_output = cell->output(c.first);
 						log_assert(is_input || is_output);
 						if (is_input) {
-							/*if (!w->port_input)*/ {
-								SigBit I = sigmap(b);
-								if (I != b)
-									alias_map[b] = I;
-								/*if (!output_bits.count(b))*/
-									co_bits.emplace_back(b, 0);
-							}
+							SigBit I = sigmap(b);
+							if (I != b)
+								alias_map[b] = I;
+							co_bits.emplace_back(b, 0);
 						}
 						if (is_output) {
 							SigBit O = sigmap(b);
-							/*if (!input_bits.count(O))*/
-								ci_bits.emplace_back(O, 0);
+							ci_bits.emplace_back(O, 0);
 						}
 					}
 				}
@@ -367,9 +361,6 @@ struct XAigerWriter
 			//co_bits.erase(bit);
 			output_bits.erase(bit);
 		}
-		// Erase all CIs that are also COs
-		//for (auto bit : co_bits)
-		//	ci_bits.erase(bit);
 		// CIs cannot be undriven
 		for (const auto &c : ci_bits)
 			undriven_bits.erase(c.first);

From 709f76c10742602f5cbc0d32805a325ecab982ee Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 16:35:27 -0700
Subject: [PATCH 29/59] Remove use of abc_box_id in stat

---
 passes/cmds/stat.cc | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index 3909c4c8c..54f4ea817 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -269,9 +269,6 @@ struct StatPass : public Pass {
 				if (mod->get_bool_attribute("\\top"))
 					top_mod = mod;
 
-			if (mod->attributes.count("\\abc_box_id"))
-				continue;
-
 			statdata_t data(design, mod, width_mode, cell_area);
 			mod_stat[mod->name] = data;
 

From a20ed260e1b12da64bc4b40682c53145f6ffe827 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 16:36:03 -0700
Subject: [PATCH 30/59] Skip if abc_box_id earlier

---
 passes/techmap/abc9.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 8b5b172ab..18f860e36 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -1402,14 +1402,14 @@ struct Abc9Pass : public Pass {
 
 		for (auto mod : design->selected_modules())
 		{
+			if (mod->attributes.count("\\abc_box_id"))
+				continue;
+
 			if (mod->processes.size() > 0) {
 				log("Skipping module %s as it contains processes.\n", log_id(mod));
 				continue;
 			}
 
-			if (mod->attributes.count("\\abc_box_id"))
-				continue;
-
 			assign_map.set(mod);
 			signal_init.clear();
 

From ed5e75ed7d5a4515e23a496570c7eb03f48742b0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 09:02:58 -0700
Subject: [PATCH 31/59] Rename to abc_*.{box,lut}

---
 techlibs/ice40/{hx.box => abc_hx.box}  | 0
 techlibs/ice40/{lp.box => abc_lp.box}  | 0
 techlibs/ice40/{lp.lut => abc_lp.lut}  | 0
 techlibs/ice40/{hx.lut => abc_lut.box} | 0
 techlibs/ice40/{u.box => abc_u.box}    | 0
 techlibs/ice40/{u.lut => abc_u.lut}    | 0
 6 files changed, 0 insertions(+), 0 deletions(-)
 rename techlibs/ice40/{hx.box => abc_hx.box} (100%)
 rename techlibs/ice40/{lp.box => abc_lp.box} (100%)
 rename techlibs/ice40/{lp.lut => abc_lp.lut} (100%)
 rename techlibs/ice40/{hx.lut => abc_lut.box} (100%)
 rename techlibs/ice40/{u.box => abc_u.box} (100%)
 rename techlibs/ice40/{u.lut => abc_u.lut} (100%)

diff --git a/techlibs/ice40/hx.box b/techlibs/ice40/abc_hx.box
similarity index 100%
rename from techlibs/ice40/hx.box
rename to techlibs/ice40/abc_hx.box
diff --git a/techlibs/ice40/lp.box b/techlibs/ice40/abc_lp.box
similarity index 100%
rename from techlibs/ice40/lp.box
rename to techlibs/ice40/abc_lp.box
diff --git a/techlibs/ice40/lp.lut b/techlibs/ice40/abc_lp.lut
similarity index 100%
rename from techlibs/ice40/lp.lut
rename to techlibs/ice40/abc_lp.lut
diff --git a/techlibs/ice40/hx.lut b/techlibs/ice40/abc_lut.box
similarity index 100%
rename from techlibs/ice40/hx.lut
rename to techlibs/ice40/abc_lut.box
diff --git a/techlibs/ice40/u.box b/techlibs/ice40/abc_u.box
similarity index 100%
rename from techlibs/ice40/u.box
rename to techlibs/ice40/abc_u.box
diff --git a/techlibs/ice40/u.lut b/techlibs/ice40/abc_u.lut
similarity index 100%
rename from techlibs/ice40/u.lut
rename to techlibs/ice40/abc_u.lut

From 8024f4189738af196f7ce432d95c73efd1f02955 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 09:04:34 -0700
Subject: [PATCH 32/59] Fix rename

---
 techlibs/ice40/{abc_lut.box => abc_hx.lut} | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename techlibs/ice40/{abc_lut.box => abc_hx.lut} (100%)

diff --git a/techlibs/ice40/abc_lut.box b/techlibs/ice40/abc_hx.lut
similarity index 100%
rename from techlibs/ice40/abc_lut.box
rename to techlibs/ice40/abc_hx.lut

From 7b6ab937c14ae30d331527c71dffbc050aaba13c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 09:05:22 -0700
Subject: [PATCH 33/59] Make SB_LUT4 a blackbox

---
 techlibs/ice40/abc_hx.box | 2 +-
 techlibs/ice40/abc_lp.box | 2 +-
 techlibs/ice40/abc_u.box  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index c31f7bf39..5a18a8423 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -9,5 +9,5 @@ SB_CARRY 1 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 1 4 1
+SB_LUT4 2 0 4 1
 449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index 7eb8e86e0..87fe81585 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -9,5 +9,5 @@ SB_CARRY 1 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 1 4 1
+SB_LUT4 2 0 4 1
 465 558 589 661
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 94df1df8f..5035a4169 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -9,5 +9,5 @@ SB_CARRY 1 1 3 1
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 1 4 1
+SB_LUT4 2 0 4 1
 1285 1231 1205 874

From 9278192efe5ae6382f4e011abaf417b45a6abfef Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 09:58:34 -0700
Subject: [PATCH 34/59] Also update Makefile.inc

---
 techlibs/ice40/Makefile.inc | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index cb2121a11..d258d5a5d 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,13 +28,12 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/lp.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/lp.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/u.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/u.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.lut))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.box))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))

From c997a77014b5d8dbfb24e77bb8157454619ea366 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 10:19:45 -0700
Subject: [PATCH 35/59] Ignore 'whitebox' attr in flatten with "-wb" option

---
 kernel/rtlil.h            |  4 ++--
 passes/techmap/techmap.cc | 24 +++++++++++++++++++-----
 2 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index c11c020c1..db0a8f762 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -575,8 +575,8 @@ struct RTLIL::AttrObject
 	void set_bool_attribute(RTLIL::IdString id);
 	bool get_bool_attribute(RTLIL::IdString id) const;
 
-	bool get_blackbox_attribute() const {
-		return get_bool_attribute("\\blackbox") || get_bool_attribute("\\whitebox");
+	bool get_blackbox_attribute(bool ignore_wb=false) const {
+		return get_bool_attribute("\\blackbox") || (!ignore_wb && get_bool_attribute("\\whitebox"));
 	}
 
 	void set_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index d694e8165..82c815e2e 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -84,6 +84,7 @@ struct TechmapWorker
 	bool flatten_mode;
 	bool recursive_mode;
 	bool autoproc_mode;
+	bool ignore_wb;
 
 	TechmapWorker()
 	{
@@ -92,6 +93,7 @@ struct TechmapWorker
 		flatten_mode = false;
 		recursive_mode = false;
 		autoproc_mode = false;
+		ignore_wb = false;
 	}
 
 	std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
@@ -472,7 +474,7 @@ struct TechmapWorker
 				RTLIL::Module *tpl = map->modules_[tpl_name];
 				std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
 
-				if (tpl->get_blackbox_attribute())
+				if (tpl->get_blackbox_attribute(ignore_wb))
 					continue;
 
 				if (!flatten_mode)
@@ -1145,7 +1147,7 @@ struct FlattenPass : public Pass {
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    flatten [selection]\n");
+		log("    flatten [options] [selection]\n");
 		log("\n");
 		log("This pass flattens the design by replacing cells by their implementation. This\n");
 		log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
@@ -1154,17 +1156,29 @@ struct FlattenPass : public Pass {
 		log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
 		log("flattened by this command.\n");
 		log("\n");
+		log("    -wb\n");
+		log("        Ignore the 'whitebox' attribute on cell implementations.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing FLATTEN pass (flatten design).\n");
 		log_push();
 
-		extra_args(args, 1, design);
-
 		TechmapWorker worker;
 		worker.flatten_mode = true;
 
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-wb") {
+				worker.ignore_wb = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+
 		std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
 		for (auto module : design->modules())
 			celltypeMap[module->name].insert(module->name);
@@ -1209,7 +1223,7 @@ struct FlattenPass : public Pass {
 
 			dict<RTLIL::IdString, RTLIL::Module*> new_modules;
 			for (auto mod : vector<Module*>(design->modules()))
-				if (used_modules[mod->name] || mod->get_blackbox_attribute()) {
+				if (used_modules[mod->name] || mod->get_blackbox_attribute(worker.ignore_wb)) {
 					new_modules[mod->name] = mod;
 				} else {
 					log("Deleting now unused module %s.\n", log_id(mod));

From 79881141e2f9354a12df81277b82e011f52994ae Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 10:30:45 -0700
Subject: [PATCH 36/59] write_json to not write contents (cells/wires) of
 whiteboxes

---
 backends/json/json.cc | 115 ++++++++++++++++++++++--------------------
 1 file changed, 59 insertions(+), 56 deletions(-)

diff --git a/backends/json/json.cc b/backends/json/json.cc
index f5c687981..b4f82a3fe 100644
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -130,72 +130,75 @@ struct JsonWriter
 			f << stringf("        }");
 			first = false;
 		}
-		f << stringf("\n      },\n");
+		f << stringf("\n      }");
 
-		f << stringf("      \"cells\": {");
-		first = true;
-		for (auto c : module->cells()) {
-			if (use_selection && !module->selected(c))
-				continue;
-			f << stringf("%s\n", first ? "" : ",");
-			f << stringf("        %s: {\n", get_name(c->name).c_str());
-			f << stringf("          \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0");
-			f << stringf("          \"type\": %s,\n", get_name(c->type).c_str());
-			if (aig_mode) {
-				Aig aig(c);
-				if (!aig.name.empty()) {
-					f << stringf("          \"model\": \"%s\",\n", aig.name.c_str());
-					aig_models.insert(aig);
+		if (!module->get_blackbox_attribute()) {
+			f << stringf(",\n      \"cells\": {");
+			first = true;
+			for (auto c : module->cells()) {
+				if (use_selection && !module->selected(c))
+					continue;
+				f << stringf("%s\n", first ? "" : ",");
+				f << stringf("        %s: {\n", get_name(c->name).c_str());
+				f << stringf("          \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0");
+				f << stringf("          \"type\": %s,\n", get_name(c->type).c_str());
+				if (aig_mode) {
+					Aig aig(c);
+					if (!aig.name.empty()) {
+						f << stringf("          \"model\": \"%s\",\n", aig.name.c_str());
+						aig_models.insert(aig);
+					}
 				}
-			}
-			f << stringf("          \"parameters\": {");
-			write_parameters(c->parameters);
-			f << stringf("\n          },\n");
-			f << stringf("          \"attributes\": {");
-			write_parameters(c->attributes);
-			f << stringf("\n          },\n");
-			if (c->known()) {
-				f << stringf("          \"port_directions\": {");
+				f << stringf("          \"parameters\": {");
+				write_parameters(c->parameters);
+				f << stringf("\n          },\n");
+				f << stringf("          \"attributes\": {");
+				write_parameters(c->attributes);
+				f << stringf("\n          },\n");
+				if (c->known()) {
+					f << stringf("          \"port_directions\": {");
+					bool first2 = true;
+					for (auto &conn : c->connections()) {
+						string direction = "output";
+						if (c->input(conn.first))
+							direction = c->output(conn.first) ? "inout" : "input";
+						f << stringf("%s\n", first2 ? "" : ",");
+						f << stringf("            %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str());
+						first2 = false;
+					}
+					f << stringf("\n          },\n");
+				}
+				f << stringf("          \"connections\": {");
 				bool first2 = true;
 				for (auto &conn : c->connections()) {
-					string direction = "output";
-					if (c->input(conn.first))
-						direction = c->output(conn.first) ? "inout" : "input";
 					f << stringf("%s\n", first2 ? "" : ",");
-					f << stringf("            %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str());
+					f << stringf("            %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str());
 					first2 = false;
 				}
-				f << stringf("\n          },\n");
+				f << stringf("\n          }\n");
+				f << stringf("        }");
+				first = false;
 			}
-			f << stringf("          \"connections\": {");
-			bool first2 = true;
-			for (auto &conn : c->connections()) {
-				f << stringf("%s\n", first2 ? "" : ",");
-				f << stringf("            %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str());
-				first2 = false;
-			}
-			f << stringf("\n          }\n");
-			f << stringf("        }");
-			first = false;
-		}
-		f << stringf("\n      },\n");
+			f << stringf("\n      },\n");
 
-		f << stringf("      \"netnames\": {");
-		first = true;
-		for (auto w : module->wires()) {
-			if (use_selection && !module->selected(w))
-				continue;
-			f << stringf("%s\n", first ? "" : ",");
-			f << stringf("        %s: {\n", get_name(w->name).c_str());
-			f << stringf("          \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0");
-			f << stringf("          \"bits\": %s,\n", get_bits(w).c_str());
-			f << stringf("          \"attributes\": {");
-			write_parameters(w->attributes);
-			f << stringf("\n          }\n");
-			f << stringf("        }");
-			first = false;
+			f << stringf("      \"netnames\": {");
+			first = true;
+			for (auto w : module->wires()) {
+				if (use_selection && !module->selected(w))
+					continue;
+				f << stringf("%s\n", first ? "" : ",");
+				f << stringf("        %s: {\n", get_name(w->name).c_str());
+				f << stringf("          \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0");
+				f << stringf("          \"bits\": %s,\n", get_bits(w).c_str());
+				f << stringf("          \"attributes\": {");
+				write_parameters(w->attributes);
+				f << stringf("\n          }\n");
+				f << stringf("        }");
+				first = false;
+			}
+			f << stringf("\n      }");
 		}
-		f << stringf("\n      }\n");
+		f << stringf("\n");
 
 		f << stringf("    }");
 	}

From 4c327cf316404fbedb1d26b0aebecaaf01d46f6b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 10:32:41 -0700
Subject: [PATCH 37/59] Use new -wb flag for ABC flow

---
 backends/aiger/xaiger.cc      | 60 ++++++++++++++++++-----------------
 techlibs/ice40/abc.v          | 12 -------
 techlibs/ice40/cells_sim.v    |  2 ++
 techlibs/ice40/synth_ice40.cc | 10 ++----
 4 files changed, 36 insertions(+), 48 deletions(-)
 delete mode 100644 techlibs/ice40/abc.v

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 582c49976..975780488 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -103,7 +103,7 @@ struct XAigerWriter
 		return aig_map.at(bit);
 	}
 
-	XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
+	XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool ignore_boxes=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
 	{
 		pool<SigBit> undriven_bits;
 		pool<SigBit> unused_bits;
@@ -177,36 +177,38 @@ struct XAigerWriter
 
 		for (auto cell : module->cells())
 		{
-			toposort.node(cell->name);
-			for (const auto &conn : cell->connections())
-			{
-				if (!cell->type.in("$_NOT_", "$_AND_")) {
-					if (yosys_celltypes.cell_known(cell->type)) {
-						if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
-							continue;
-						if (cell->type == "$memrd" && conn.first == "\\DATA")
+			if (!ignore_boxes) {
+				toposort.node(cell->name);
+				for (const auto &conn : cell->connections())
+				{
+					if (!cell->type.in("$_NOT_", "$_AND_")) {
+						if (yosys_celltypes.cell_known(cell->type)) {
+							if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
+								continue;
+							if (cell->type == "$memrd" && conn.first == "\\DATA")
+								continue;
+						}
+
+						RTLIL::Module* inst_module = module->design->module(cell->type);
+						log_assert(inst_module);
+						RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
+						log_assert(inst_module_port);
+
+						if (inst_module_port->attributes.count("\\abc_flop_q"))
 							continue;
 					}
 
-					RTLIL::Module* inst_module = module->design->module(cell->type);
-					log_assert(inst_module);
-					RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
-					log_assert(inst_module_port);
+					if (cell->input(conn.first)) {
+						// Ignore inout for the sake of topographical ordering
+						if (cell->output(conn.first)) continue;
+						for (auto bit : sigmap(conn.second))
+							bit_users[bit].insert(cell->name);
+					}
 
-					if (inst_module_port->attributes.count("\\abc_flop_q"))
-						continue;
+					if (cell->output(conn.first))
+						for (auto bit : sigmap(conn.second))
+							bit_drivers[bit].insert(cell->name);
 				}
-
-				if (cell->input(conn.first)) {
-					// Ignore inout for the sake of topographical ordering
-					if (cell->output(conn.first)) continue;
-					for (auto bit : sigmap(conn.second))
-						bit_users[bit].insert(cell->name);
-				}
-
-				if (cell->output(conn.first))
-					for (auto bit : sigmap(conn.second))
-						bit_drivers[bit].insert(cell->name);
 			}
 
 			if (cell->type == "$_NOT_")
@@ -249,7 +251,7 @@ struct XAigerWriter
 			//	continue;
 			//}
 
-			RTLIL::Module* box_module = module->design->module(cell->type);
+			RTLIL::Module* box_module = !ignore_boxes ? module->design->module(cell->type) : nullptr;
 			if (!box_module || !box_module->attributes.count("\\abc_box_id")) {
 				for (const auto &c : cell->connections()) {
 					if (c.second.is_fully_const()) continue;
@@ -705,12 +707,12 @@ struct XAigerWriter
 				RTLIL::Selection& sel = holes_module->design->selection_stack.back();
 				sel.select(holes_module);
 
-				Pass::call(holes_module->design, "flatten; aigmap");
+				Pass::call(holes_module->design, "flatten -wb; aigmap");
 
 				holes_module->design->selection_stack.pop_back();
 
 				std::stringstream a_buffer;
-				XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, false /*bmode*/);
+				XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, false /*bmode*/, true /* ignore_boxes */);
 				writer.write_aiger(a_buffer, false /*ascii_mode*/, false /*miter_mode*/, false /*symbols_mode*/, false /*omode*/);
 
 				f << "a";
diff --git a/techlibs/ice40/abc.v b/techlibs/ice40/abc.v
deleted file mode 100644
index e2a54a42c..000000000
--- a/techlibs/ice40/abc.v
+++ /dev/null
@@ -1,12 +0,0 @@
-(* abc_box_id = 1 *)
-module SB_CARRY (output CO, input CI, I0, I1);
-	assign CO = (I0 && I1) || ((I0 || I1) && CI);
-endmodule
-
-(* abc_box_id = 2 *)
-module SB_LUT4 (output O, input I0, I1, I2, I3);
-	parameter [15:0] LUT_INIT = 0;
-	// Indicate this is a black-box
-	assign O = 1'b0;
-endmodule
-
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 70cd51ed1..dba563e37 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -118,6 +118,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
+(* abc_box_id = 2 *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -126,6 +127,7 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
+(* abc_box_id = 1, whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 7c95588e4..84abf7181 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib +/ice40/cells_sim.v");
+			run("read_verilog -wb +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -327,12 +327,8 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
 			}
 			if (!noabc) {
-				if (abc == "abc9") {
-					run("read_verilog +/ice40/abc.v");
-					run("techmap -map +/techmap.v A:abc_box_id");
-					run(abc + stringf(" -dress -lut +/ice40/%s.lut -box +/ice40/%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
-					run("blackbox A:abc_box_id");
-				}
+				if (abc == "abc9")
+					run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
 				else
 					run(abc + " -lut 4", "(skip if -noabc)");
 			}

From b531efd6d9febe679571c897a8e22dbeaedeb96e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 17:35:16 -0700
Subject: [PATCH 38/59] Spelling

---
 backends/aiger/aiger.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index dfe506c66..516e538a5 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -685,7 +685,7 @@ struct AigerBackend : public Backend {
 		log("invariant constraints.\n");
 		log("\n");
 		log("    -ascii\n");
-		log("        write ASCII version of AGIER format\n");
+		log("        write ASCII version of AIGER format\n");
 		log("\n");
 		log("    -zinit\n");
 		log("        convert FFs to zero-initialized FFs, adding additional inputs for\n");

From 21701cc1df461a77d39afaddf0f31ab78f307e32 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 17:39:36 -0700
Subject: [PATCH 39/59] read_aiger to parse 'r' extension

---
 frontends/aiger/aigerparse.cc | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 9c8cee63a..db5f9d2b9 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -363,6 +363,24 @@ void AigerReader::parse_xaiger()
                     module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
                 }
             }
+            else if (c == 'r') {
+                uint32_t dataSize = parse_xaiger_literal(f);
+                uint32_t flopNum = parse_xaiger_literal(f);
+                f.ignore(flopNum * sizeof(uint32_t));
+                log_assert(inputs.size() >= flopNum);
+                for (auto it = inputs.end() - flopNum; it != inputs.end(); ++it) {
+                    log_assert((*it)->port_input);
+                    (*it)->port_input = false;
+                }
+                inputs.erase(inputs.end() - flopNum, inputs.end());
+                log_assert(outputs.size() >= flopNum);
+                for (auto it = outputs.end() - flopNum; it != outputs.end(); ++it) {
+                    log_assert((*it)->port_output);
+                    (*it)->port_output = false;
+                }
+                outputs.erase(outputs.end() - flopNum, outputs.end());
+                module->fixup_ports();
+            }
             else if (c == 'n') {
                parse_xaiger_literal(f);
                f >> s;

From 6bdf98d591a4ee5752d687d35238b454288e1d96 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 17:43:13 -0700
Subject: [PATCH 40/59] Add flop support for write_xaiger

---
 backends/aiger/xaiger.cc | 94 +++++++++++++++++++++++++++++++++++-----
 1 file changed, 83 insertions(+), 11 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 975780488..587294a40 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -50,6 +50,7 @@ struct XAigerWriter
 	dict<SigBit, pair<SigBit, SigBit>> and_map;
 	//pool<SigBit> initstate_bits;
 	vector<std::pair<SigBit,int>> ci_bits, co_bits;
+	vector<std::pair<SigBit,SigBit>> ff_bits;
 
 	vector<pair<int, int>> aig_gates;
 	vector<int> aig_latchin, aig_latchinit, aig_outputs;
@@ -177,6 +178,9 @@ struct XAigerWriter
 
 		for (auto cell : module->cells())
 		{
+			RTLIL::Module* inst_module = module->design->module(cell->type);
+			bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
+
 			if (!ignore_boxes) {
 				toposort.node(cell->name);
 				for (const auto &conn : cell->connections())
@@ -189,7 +193,6 @@ struct XAigerWriter
 								continue;
 						}
 
-						RTLIL::Module* inst_module = module->design->module(cell->type);
 						log_assert(inst_module);
 						RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
 						log_assert(inst_module_port);
@@ -251,8 +254,32 @@ struct XAigerWriter
 			//	continue;
 			//}
 
-			RTLIL::Module* box_module = !ignore_boxes ? module->design->module(cell->type) : nullptr;
-			if (!box_module || !box_module->attributes.count("\\abc_box_id")) {
+			log_assert(inst_module);
+			if (inst_flop) {
+				SigBit d, q;
+				for (const auto &c : cell->connections()) {
+					for (auto b : c.second.bits()) {
+						auto is_input = cell->input(c.first);
+						auto is_output = cell->output(c.first);
+						log_assert(is_input || is_output);
+						if (is_input && inst_module->wire(c.first)->attributes.count("\\abc_flop_d")) {
+							SigBit I = sigmap(b);
+							if (I != b)
+								alias_map[b] = I;
+							d = b;
+						}
+						if (is_output && inst_module->wire(c.first)->attributes.count("\\abc_flop_q")) {
+						    SigBit O = sigmap(b);
+							q = O;
+						}
+					}
+				}
+				if (!abc_box_seen) abc_box_seen = inst_module->attributes.count("\\abc_box_id");
+
+				ff_bits.emplace_back(d, q);
+				undriven_bits.erase(q);
+			}
+			else if (!inst_module->attributes.count("\\abc_box_id")) {
 				for (const auto &c : cell->connections()) {
 					if (c.second.is_fully_const()) continue;
 					for (auto b : c.second.bits()) {
@@ -311,6 +338,7 @@ struct XAigerWriter
 				if (!box_module || !box_module->attributes.count("\\abc_box_id"))
 					continue;
 
+				// Box ordering is alphabetical
 				cell->connections_.sort(RTLIL::sort_by_id_str());
 				for (const auto &c : cell->connections()) {
 					for (auto b : c.second.bits()) {
@@ -394,10 +422,20 @@ struct XAigerWriter
 			aig_map[bit] = 2*aig_m;
 		}
 
+		for (auto &f : ff_bits) {
+			auto bit = f.second;
+			aig_m++, aig_i++;
+			aig_map[bit] = 2*aig_m;
+		}
+
+		dict<SigBit, int> ff_aig_map;
 		for (auto &c : ci_bits) {
 			aig_m++, aig_i++;
 			c.second = 2*aig_m;
-			aig_map[c.first] = c.second;
+			auto r = aig_map.insert(std::make_pair(c.first, c.second));
+			if (!r.second) {
+				ff_aig_map[c.first] = c.second;
+			}
 		}
 
 		if (imode && input_bits.empty()) {
@@ -472,6 +510,12 @@ struct XAigerWriter
 			aig_outputs.push_back(bit2aig(bit));
 		}
 
+		for (auto &f : ff_bits) {
+			auto bit = f.second;
+			aig_o++;
+			aig_outputs.push_back(ff_aig_map.at(f.second));
+		}
+
 		if (omode && output_bits.empty()) {
 			aig_o++;
 			aig_outputs.push_back(0);
@@ -629,7 +673,7 @@ struct XAigerWriter
 
 		f << "c";
 
-		if (!box_list.empty()) {
+		if (!box_list.empty() || !ff_bits.empty()) {
 			std::stringstream h_buffer;
 			auto write_h_buffer = [&h_buffer](int i32) {
 				// TODO: Don't assume we're on little endian
@@ -644,10 +688,10 @@ struct XAigerWriter
 			if (omode && num_outputs == 0)
 				num_outputs = 1;
 			write_h_buffer(1);
-			write_h_buffer(input_bits.size() + ci_bits.size());
-			write_h_buffer(num_outputs + co_bits.size());
-			write_h_buffer(input_bits.size());
-			write_h_buffer(num_outputs);
+			write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
+			write_h_buffer(num_outputs + ff_bits.size() + co_bits.size());
+			write_h_buffer(input_bits.size() + ff_bits.size());
+			write_h_buffer(num_outputs + ff_bits.size());
 			write_h_buffer(box_list.size());
 
 			RTLIL::Module *holes_module = nullptr;
@@ -700,6 +744,34 @@ struct XAigerWriter
 			f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
 			f.write(buffer_str.data(), buffer_str.size());
 
+			if (!ff_bits.empty()) {
+				std::stringstream r_buffer;
+				auto write_r_buffer = [&r_buffer](int i32) {
+					// TODO: Don't assume we're on little endian
+#ifdef _WIN32
+					int i32_be = _byteswap_ulong(i32);
+#else
+					int i32_be = __builtin_bswap32(i32);
+#endif
+					r_buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
+				};
+				write_r_buffer(ff_bits.size());
+				int mergeability_class = 1;
+				for (auto cell : ff_bits)
+					write_r_buffer(mergeability_class++);
+
+				f << "r";
+				std::string buffer_str = r_buffer.str();
+				// TODO: Don't assume we're on little endian
+#ifdef _WIN32
+				int buffer_size_be = _byteswap_ulong(buffer_str.size());
+#else
+				int buffer_size_be = __builtin_bswap32(buffer_str.size());
+#endif
+				f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
+				f.write(buffer_str.data(), buffer_str.size());
+			}
+
 			if (holes_module) {
 				holes_module->fixup_ports();
 
@@ -792,7 +864,7 @@ struct XAigerWriter
 			RTLIL::SigBit b = c.first;
 			RTLIL::Wire *wire = b.wire;
 			int i = b.offset;
-			int a = c.second;
+			int a = bit2aig(b);
 			log_assert((a & 1) == 0);
 			input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
 		}
@@ -845,7 +917,7 @@ struct XAigerBackend : public Backend {
 		log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
 		log("\n");
 		log("    -ascii\n");
-		log("        write ASCII version of AGIER format\n");
+		log("        write ASCII version of AIGER format\n");
 		log("\n");
 		log("    -zinit\n");
 		log("        convert FFs to zero-initialized FFs, adding additional inputs for\n");

From ca1eb98a975e1d95629f8e55bfdd021221edf0b7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 17:46:32 -0700
Subject: [PATCH 41/59] Add SB_DFF* to boxes

---
 techlibs/ice40/abc_hx.box | 104 +++++++++++++++++++++++++++++++++++++-
 techlibs/ice40/abc_lp.box | 104 +++++++++++++++++++++++++++++++++++++-
 techlibs/ice40/abc_u.box  | 104 +++++++++++++++++++++++++++++++++++++-
 3 files changed, 306 insertions(+), 6 deletions(-)

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 5a18a8423..9ebdae18b 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -2,12 +2,112 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
+# Inputs: C D
+# Outputs: Q
+SB_DFF 1 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFE 2 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFSR 3 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFR 4 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFSS 5 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFS 6 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFESR 7 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFER 8 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFESS 9 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFES 10 0 4 1
+- - - -
+
+# Inputs: C D
+# Outputs: Q
+SB_DFFN 11 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFNE 12 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNSR 13 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNR 14 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNSS 15 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNS 16 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNESR 17 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNER 18 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNESS 19 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNES 20 0 4 1
+- - - -
+
 # Inputs: CI I0 I1
 # Outputs: CO
-SB_CARRY 1 1 3 1
+SB_CARRY 21 1 3 1
 126 259 231
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 0 4 1
+SB_LUT4 22 0 4 1
 449 400 379 316
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index 87fe81585..464821dac 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -2,12 +2,112 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
+# Inputs: C D
+# Outputs: Q
+SB_DFF 1 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFE 2 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFSR 3 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFR 4 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFSS 5 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFS 6 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFESR 7 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFER 8 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFESS 9 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFES 10 0 4 1
+- - - -
+
+# Inputs: C D
+# Outputs: Q
+SB_DFFN 11 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFNE 12 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNSR 13 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNR 14 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNSS 15 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNS 16 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNESR 17 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNER 18 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNESS 19 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNES 20 0 4 1
+- - - -
+
 # Inputs: CI I0 I1
 # Outputs: CO
-SB_CARRY 1 1 3 1
+SB_CARRY 21 1 3 1
 186 675 609
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 0 4 1
+SB_LUT4 22 0 4 1
 465 558 589 661
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 5035a4169..314bff401 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -2,12 +2,112 @@
 
 # NB: Inputs/Outputs must be ordered alphabetically
 
+# Inputs: C D
+# Outputs: Q
+SB_DFF 1 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFE 2 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFSR 3 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFR 4 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFSS 5 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFS 6 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFESR 7 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFER 8 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFESS 9 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFES 10 0 4 1
+- - - -
+
+# Inputs: C D
+# Outputs: Q
+SB_DFFN 11 0 2 1
+- -
+
+# Inputs: C D E
+# Outputs: Q
+SB_DFFNE 12 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNSR 13 0 3 1
+- - -
+
+# Inputs: C D R
+# Outputs: Q
+SB_DFFNR 14 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNSS 15 0 3 1
+- - -
+
+# Inputs: C D S
+# Outputs: Q
+SB_DFFNS 16 0 3 1
+- - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNESR 17 0 4 1
+- - - -
+
+# Inputs: C D E R
+# Outputs: Q
+SB_DFFNER 18 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNESS 19 0 4 1
+- - - -
+
+# Inputs: C D E S
+# Outputs: Q
+SB_DFFNES 20 0 4 1
+- - - -
+
 # Inputs: CI I0 I1
 # Outputs: CO
-SB_CARRY 1 1 3 1
+SB_CARRY 21 1 3 1
 278 675 609
 
 # Inputs: I0 I1 I2 I3
 # Outputs: O
-SB_LUT4 2 0 4 1
+SB_LUT4 22 0 4 1
 1285 1231 1205 874

From cf66416110f60b7dce10a78960898ceb52f51626 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 17:46:53 -0700
Subject: [PATCH 42/59] Annotate SB_DFF* with abc_flop and abc_box_id

---
 techlibs/ice40/cells_sim.v | 71 ++++++++++++++++++++++++++------------
 1 file changed, 49 insertions(+), 22 deletions(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index dba563e37..a6f1fc9de 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -118,7 +118,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 2 *)
+(* abc_box_id = 22 *
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
@@ -127,25 +127,35 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 1, whitebox *)
+(* abc_box_id = 21, whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
+(* abc_box_id = 1, abc_flop *)
+`ifdef ABC_FLOPS
+    (* whitebox *)
+`endif
+module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
+`ifndef ABC_FLOPS
 	always @(posedge C)
 		Q <= D;
+`else
+    assign Q = D;
+`endif
 endmodule
 
-module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
+//(* abc_box_id = 2, abc_flop *)
+module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 3, abc_flop *)
+module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (R)
 			Q <= 0;
@@ -153,7 +163,8 @@ module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 4, abc_flop *)
+module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -161,7 +172,8 @@ module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 5, abc_flop *)
+module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (S)
 			Q <= 1;
@@ -169,7 +181,8 @@ module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 6, abc_flop *)
+module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -177,7 +190,8 @@ module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 7, abc_flop *)
+module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (E) begin
 			if (R)
@@ -187,7 +201,8 @@ module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 8, abc_flop *)
+module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(posedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -195,7 +210,8 @@ module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 9, abc_flop *)
+module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(posedge C)
 		if (E) begin
 			if (S)
@@ -205,7 +221,8 @@ module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 10, abc_flop *)
+module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(posedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -215,18 +232,21 @@ endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
-module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
+//(* abc_box_id = 11, abc_flop *)
+module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
 	always @(negedge C)
 		Q <= D;
 endmodule
 
-module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
+//(* abc_box_id = 12, abc_flop *)
+module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (E)
 			Q <= D;
 endmodule
 
-module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 13, abc_flop *)
+module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (R)
 			Q <= 0;
@@ -234,7 +254,8 @@ module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
+//(* abc_box_id = 14, abc_flop *)
+module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -242,7 +263,8 @@ module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 15, abc_flop *)
+module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (S)
 			Q <= 1;
@@ -250,7 +272,8 @@ module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
+//(* abc_box_id = 16, abc_flop *)
+module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;
@@ -258,7 +281,8 @@ module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 17, abc_flop *)
+module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (E) begin
 			if (R)
@@ -268,7 +292,8 @@ module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 		end
 endmodule
 
-module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
+//(* abc_box_id = 18, abc_flop *)
+module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
 	always @(negedge C, posedge R)
 		if (R)
 			Q <= 0;
@@ -276,7 +301,8 @@ module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 			Q <= D;
 endmodule
 
-module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 19, abc_flop *)
+module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(negedge C)
 		if (E) begin
 			if (S)
@@ -286,7 +312,8 @@ module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 		end
 endmodule
 
-module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
+//(* abc_box_id = 20, abc_flop *)
+module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
 	always @(negedge C, posedge S)
 		if (S)
 			Q <= 1;

From 0919f36b88bed88e6dbfa23381540dc8ee035962 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 17:50:11 -0700
Subject: [PATCH 43/59] Missing close bracket

---
 techlibs/ice40/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index a6f1fc9de..1d104c5d7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -118,7 +118,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 22 *
+(* abc_box_id = 22 *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];

From 19b660ff6e8b493ff3de43ce59e393c56b9a6b3b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Apr 2019 23:07:16 -0700
Subject: [PATCH 44/59] Fix SB_DFF comb model

---
 techlibs/ice40/cells_sim.v    | 2 +-
 techlibs/ice40/synth_ice40.cc | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 1d104c5d7..c49b29ab3 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -143,7 +143,7 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in
 	always @(posedge C)
 		Q <= D;
 `else
-    assign Q = D;
+    always @* Q = D;
 `endif
 endmodule
 
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 84abf7181..d5d354701 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -wb +/ice40/cells_sim.v");
+			run("read_verilog -wb -D ABC_FLOPS +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -293,7 +293,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap");
 			else
 				run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
-			if (retime || help_mode)
+			if ((retime || help_mode) && abc != "abc9")
 				run(abc + " -dff", "(only if -retime)");
 			run("ice40_opt");
 		}

From 2776925bcf04e67d1c33812e102d1195dca393bf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Apr 2019 08:36:38 -0700
Subject: [PATCH 45/59] Make SB_DFF whitebox

---
 techlibs/ice40/abc_hx.box | 2 +-
 techlibs/ice40/abc_lp.box | 2 +-
 techlibs/ice40/abc_u.box  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index 9ebdae18b..994f3091d 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 0 2 1
+SB_DFF 1 1 2 1
 - -
 
 # Inputs: C D E
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index 464821dac..002b7bba4 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 0 2 1
+SB_DFF 1 1 2 1
 - -
 
 # Inputs: C D E
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 314bff401..cb336181c 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -4,7 +4,7 @@
 
 # Inputs: C D
 # Outputs: Q
-SB_DFF 1 0 2 1
+SB_DFF 1 1 2 1
 - -
 
 # Inputs: C D E

From 3544a7cd7b6b2595d25c56c5b1c3fbf6c9cccf7e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Apr 2019 08:37:10 -0700
Subject: [PATCH 46/59] ignore_boxes -> holes_mode

---
 backends/aiger/xaiger.cc | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 587294a40..71aaebfd9 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -104,7 +104,7 @@ struct XAigerWriter
 		return aig_map.at(bit);
 	}
 
-	XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool ignore_boxes=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
+	XAigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool holes_mode=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
 	{
 		pool<SigBit> undriven_bits;
 		pool<SigBit> unused_bits;
@@ -181,7 +181,7 @@ struct XAigerWriter
 			RTLIL::Module* inst_module = module->design->module(cell->type);
 			bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
 
-			if (!ignore_boxes) {
+			if (!holes_mode) {
 				toposort.node(cell->name);
 				for (const auto &conn : cell->connections())
 				{
@@ -398,7 +398,7 @@ struct XAigerWriter
 		for (auto bit : unused_bits)
 			undriven_bits.erase(bit);
 
-		if (!undriven_bits.empty()) {
+		if (!undriven_bits.empty() && !holes_mode) {
 			undriven_bits.sort();
 			for (auto bit : undriven_bits) {
 				log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
@@ -511,7 +511,6 @@ struct XAigerWriter
 		}
 
 		for (auto &f : ff_bits) {
-			auto bit = f.second;
 			aig_o++;
 			aig_outputs.push_back(ff_aig_map.at(f.second));
 		}
@@ -779,12 +778,12 @@ struct XAigerWriter
 				RTLIL::Selection& sel = holes_module->design->selection_stack.back();
 				sel.select(holes_module);
 
-				Pass::call(holes_module->design, "flatten -wb; aigmap");
+				Pass::call(holes_module->design, "flatten -wb; aigmap; clean -purge");
 
 				holes_module->design->selection_stack.pop_back();
 
 				std::stringstream a_buffer;
-				XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, false /*bmode*/, true /* ignore_boxes */);
+				XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, false /*bmode*/, true /* holes_mode */);
 				writer.write_aiger(a_buffer, false /*ascii_mode*/, false /*miter_mode*/, false /*symbols_mode*/, false /*omode*/);
 
 				f << "a";

From 35f44f3ae8618b5e5da068c3df3d35b2fdc3d1aa Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Apr 2019 08:44:53 -0700
Subject: [PATCH 47/59] Do not assume inst_module is always present

---
 backends/aiger/xaiger.cc | 21 +++++++++------------
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 71aaebfd9..31b74f9aa 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -193,12 +193,13 @@ struct XAigerWriter
 								continue;
 						}
 
-						log_assert(inst_module);
-						RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
-						log_assert(inst_module_port);
+						if (inst_module) {
+							RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
+							log_assert(inst_module_port);
 
-						if (inst_module_port->attributes.count("\\abc_flop_q"))
-							continue;
+							if (inst_module_port->attributes.count("\\abc_flop_q"))
+								continue;
+						}
 					}
 
 					if (cell->input(conn.first)) {
@@ -254,7 +255,6 @@ struct XAigerWriter
 			//	continue;
 			//}
 
-			log_assert(inst_module);
 			if (inst_flop) {
 				SigBit d, q;
 				for (const auto &c : cell->connections()) {
@@ -279,7 +279,7 @@ struct XAigerWriter
 				ff_bits.emplace_back(d, q);
 				undriven_bits.erase(q);
 			}
-			else if (!inst_module->attributes.count("\\abc_box_id")) {
+			else if (inst_module && !inst_module->attributes.count("\\abc_box_id")) {
 				for (const auto &c : cell->connections()) {
 					if (c.second.is_fully_const()) continue;
 					for (auto b : c.second.bits()) {
@@ -386,15 +386,12 @@ struct XAigerWriter
 		}
 
 		// Do some CI/CO post-processing:
-		// Erase all POs and COs that are undriven
-		for (auto bit : undriven_bits) {
-			//co_bits.erase(bit);
+		// Erase all POs that are undriven
+		for (auto bit : undriven_bits)
 			output_bits.erase(bit);
-		}
 		// CIs cannot be undriven
 		for (const auto &c : ci_bits)
 			undriven_bits.erase(c.first);
-
 		for (auto bit : unused_bits)
 			undriven_bits.erase(bit);
 

From 76bba4918205445e9129895f071d35e42e23efec Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Apr 2019 15:47:36 -0700
Subject: [PATCH 48/59] Fixes for simple_abc9 tests

---
 backends/aiger/xaiger.cc | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 31b74f9aa..e93fd35f7 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -180,13 +180,14 @@ struct XAigerWriter
 		{
 			RTLIL::Module* inst_module = module->design->module(cell->type);
 			bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
+			bool known_type = yosys_celltypes.cell_known(cell->type);
 
 			if (!holes_mode) {
 				toposort.node(cell->name);
 				for (const auto &conn : cell->connections())
 				{
 					if (!cell->type.in("$_NOT_", "$_AND_")) {
-						if (yosys_celltypes.cell_known(cell->type)) {
+						if (known_type) {
 							if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
 								continue;
 							if (cell->type == "$memrd" && conn.first == "\\DATA")
@@ -279,7 +280,10 @@ struct XAigerWriter
 				ff_bits.emplace_back(d, q);
 				undriven_bits.erase(q);
 			}
-			else if (inst_module && !inst_module->attributes.count("\\abc_box_id")) {
+			else if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
+				abc_box_seen = true;
+			}
+			else {
 				for (const auto &c : cell->connections()) {
 					if (c.second.is_fully_const()) continue;
 					for (auto b : c.second.bits()) {
@@ -305,8 +309,6 @@ struct XAigerWriter
 					}
 				}
 			}
-			else
-				abc_box_seen = true;
 
 			//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
 		}
@@ -381,6 +383,8 @@ struct XAigerWriter
 					and_map[new_bit] = and_map.at(bit);
 				else if (alias_map.count(bit))
 					alias_map[new_bit] = alias_map.at(bit);
+				else
+					alias_map[new_bit] = bit;
 				output_bits.insert(new_bit);
 			}
 		}

From 59c993e4372df1624b538bd12aee96381c874f6f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Apr 2019 15:47:53 -0700
Subject: [PATCH 49/59] Select to find union of both sets on stack

---
 tests/simple_abc9/run-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index af003d52e..97f284378 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -19,4 +19,4 @@ fi
 
 cp ../simple/*.v .
 DOLLAR='?'
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_'"
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"

From af4652522fd01aaec84664e65d7fe1474c578c49 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Apr 2019 21:09:55 -0700
Subject: [PATCH 50/59] ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL
 set

---
 techlibs/ice40/cells_sim.v    | 9 ++++++---
 techlibs/ice40/synth_ice40.cc | 2 +-
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index c49b29ab3..a98bc30d9 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,10 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21, whitebox *)
+(* abc_box_id = 21 *)
+`ifdef ABC_MODEL
+    (* whitebox *)
+`endif
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
@@ -135,11 +138,11 @@ endmodule
 // Positive Edge SiliconBlue FF Cells
 
 (* abc_box_id = 1, abc_flop *)
-`ifdef ABC_FLOPS
+`ifdef ABC_MODEL
     (* whitebox *)
 `endif
 module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
-`ifndef ABC_FLOPS
+`ifndef ABC_MODEL
 	always @(posedge C)
 		Q <= D;
 `else
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index d5d354701..7cedecdff 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -wb -D ABC_FLOPS +/ice40/cells_sim.v");
+			run("read_verilog -wb -D ABC_MODEL +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}

From d7f0700bae9785a55353ca76fe9f354ee4ffe03e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 21 Apr 2019 15:19:02 -0700
Subject: [PATCH 51/59] Convert to use #945

---
 techlibs/ice40/cells_sim.v    | 10 ++--------
 techlibs/ice40/synth_ice40.cc |  2 +-
 2 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index a98bc30d9..93d970762 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,20 +127,14 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
 	assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21 *)
-`ifdef ABC_MODEL
-    (* whitebox *)
-`endif
+(* abc_box_id = 21, lib_whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
 // Positive Edge SiliconBlue FF Cells
 
-(* abc_box_id = 1, abc_flop *)
-`ifdef ABC_MODEL
-    (* whitebox *)
-`endif
+(* abc_box_id = 1, abc_flop, lib_whitebox *)
 module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
 `ifndef ABC_MODEL
 	always @(posedge C)
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 7cedecdff..718f9d9e0 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -wb -D ABC_MODEL +/ice40/cells_sim.v");
+			run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}

From 0f0ada13f46fdc00a6f55f649647c177b4a150ff Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 15:26:20 +0200
Subject: [PATCH 52/59] Add full_pmux feature to pmux2shiftx

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/opt/pmux2shiftx.cc | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc
index 5f897b131..29870f510 100644
--- a/passes/opt/pmux2shiftx.cc
+++ b/passes/opt/pmux2shiftx.cc
@@ -369,6 +369,7 @@ struct Pmux2ShiftxPass : public Pass {
 
 				dict<SigSpec, pool<int>> seldb;
 
+				SigSpec A = cell->getPort("\\A");
 				SigSpec B = cell->getPort("\\B");
 				SigSpec S = sigmap(cell->getPort("\\S"));
 				for (int i = 0; i < GetSize(S); i++)
@@ -419,6 +420,8 @@ struct Pmux2ShiftxPass : public Pass {
 						choices[val] = i;
 					}
 
+					bool full_pmux = GetSize(choices) == GetSize(S);
+
 					// TBD: also find choices that are using signals that are subsets of the bits in "sig"
 
 					if (!verbose)
@@ -634,7 +637,21 @@ struct Pmux2ShiftxPass : public Pass {
 					log("    range density: %d%%\n", range_density);
 					log("    absolute density: %d%%\n", absolute_density);
 
-					bool full_case = (min_choice == 0) && (max_choice == (1 << GetSize(sig))-1) && (max_choice+1 == GetSize(choices));
+					if (full_pmux) {
+						int full_density = 100*GetSize(choices) / (1 << GetSize(sig));
+						log("    full density: %d%%\n", full_density);
+						if (full_density < min_density) {
+							full_pmux = false;
+						} else {
+							min_choice = 0;
+							max_choice = (1 << GetSize(sig))-1;
+							log("    update to full case.\n");
+							log("    new min choice: %d\n", min_choice);
+							log("    new max choice: %d\n", max_choice);
+						}
+					}
+
+					bool full_case = (min_choice == 0) && (max_choice == (1 << GetSize(sig))-1) && (full_pmux || max_choice+1 == GetSize(choices));
 					log("    full case: %s\n", full_case ? "true" : "false");
 
 					// check density percentages
@@ -677,6 +694,10 @@ struct Pmux2ShiftxPass : public Pass {
 
 					// create data signal
 					SigSpec data(State::Sx, (max_choice+1)*extwidth);
+					if (full_pmux) {
+						for (int i = 0; i <= max_choice; i++)
+							data.replace(i*extwidth, A);
+					}
 					for (auto &it : perm_choices) {
 						int position = it.first.as_int()*extwidth;
 						int data_index = it.second;

From a80e74dc2057b175a99d5cbc2926b712f0323010 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 16:17:43 +0200
Subject: [PATCH 53/59] Updaye pmux2shiftx test

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/various/pmux2shiftx.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/various/pmux2shiftx.ys b/tests/various/pmux2shiftx.ys
index 6bb9626eb..deb134083 100644
--- a/tests/various/pmux2shiftx.ys
+++ b/tests/various/pmux2shiftx.ys
@@ -9,8 +9,8 @@ opt
 stat
 # show -width
 select -assert-count 1 t:$sub
-select -assert-count 2 t:$mux
-select -assert-count 2 t:$shift
+select -assert-count 1 t:$mux
+select -assert-count 1 t:$shift
 select -assert-count 3 t:$shiftx
 
 design -stash gate

From e158ea20979165c1bac4c5c4027cf53255e57baa Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 17:25:52 +0200
Subject: [PATCH 54/59] Add log_debug() framework

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/aiger/aigerparse.cc |  2 -
 kernel/driver.cc              |  8 +++-
 kernel/log.cc                 |  7 ++++
 kernel/log.h                  | 43 +++++++++++++++++++
 kernel/register.cc            |  1 +
 passes/cmds/trace.cc          | 34 +++++++++++++++
 passes/opt/opt_clean.cc       | 11 ++---
 passes/opt/opt_expr.cc        | 79 ++++++++++++++++++++---------------
 passes/opt/opt_merge.cc       |  8 ++--
 passes/opt/opt_muxtree.cc     |  6 +--
 passes/techmap/techmap.cc     | 37 +++++++++++++---
 11 files changed, 183 insertions(+), 53 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index cf7950c85..2e4774dfd 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -33,8 +33,6 @@
 
 YOSYS_NAMESPACE_BEGIN
 
-#define log_debug log
-
 AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name)
     : design(design), f(f), clk_name(clk_name)
 {
diff --git a/kernel/driver.cc b/kernel/driver.cc
index c539ba569..1bc7a5935 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -295,6 +295,9 @@ int main(int argc, char **argv)
 		printf("    -E <depsfile>\n");
 		printf("        write a Makefile dependencies file with in- and output file names\n");
 		printf("\n");
+		printf("    -g\n");
+		printf("        globally enable debug log messages\n");
+		printf("\n");
 		printf("    -V\n");
 		printf("        print version information and exit\n");
 		printf("\n");
@@ -315,7 +318,7 @@ int main(int argc, char **argv)
 	}
 
 	int opt;
-	while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:D:P:E:")) != -1)
+	while ((opt = getopt(argc, argv, "MXAQTVSgm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:D:P:E:")) != -1)
 	{
 		switch (opt)
 		{
@@ -340,6 +343,9 @@ int main(int argc, char **argv)
 		case 'S':
 			passes_commands.push_back("synth");
 			break;
+		case 'g':
+			log_force_debug++;
+			break;
 		case 'm':
 			plugin_filenames.push_back(optarg);
 			break;
diff --git a/kernel/log.cc b/kernel/log.cc
index 400a549dd..9a9104e26 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -56,6 +56,10 @@ int log_verbose_level;
 string log_last_error;
 void (*log_error_atexit)() = NULL;
 
+int log_make_debug = 0;
+int log_force_debug = 0;
+int log_debug_suppressed = 0;
+
 vector<int> header_count;
 pool<RTLIL::IdString> log_id_cache;
 vector<shared_str> string_buf;
@@ -92,6 +96,9 @@ void logv(const char *format, va_list ap)
 		format++;
 	}
 
+	if (log_make_debug && !ys_debug(1))
+		return;
+
 	std::string str = vstringf(format, ap);
 
 	if (str.empty())
diff --git a/kernel/log.h b/kernel/log.h
index 759939025..e6afae716 100644
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -64,6 +64,10 @@ extern int log_verbose_level;
 extern string log_last_error;
 extern void (*log_error_atexit)();
 
+extern int log_make_debug;
+extern int log_force_debug;
+extern int log_debug_suppressed;
+
 void logv(const char *format, va_list ap);
 void logv_header(RTLIL::Design *design, const char *format, va_list ap);
 void logv_warning(const char *format, va_list ap);
@@ -82,6 +86,45 @@ YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf,
 void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4), noreturn);
 YS_NORETURN void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn);
 
+#ifndef NDEBUG
+static inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; }
+#  define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)
+#else
+static inline bool ys_debug(int n = 0) { return false; }
+#  define log_debug(_fmt, ...) do { } while (0)
+#endif
+
+static inline void log_suppressed() {
+	if (log_debug_suppressed && !log_make_debug) {
+		log("<suppressed ~%d debug messages>\n", log_debug_suppressed);
+		log_debug_suppressed = 0;
+	}
+}
+
+struct LogMakeDebugHdl {
+	bool status = false;
+	LogMakeDebugHdl(bool start_on = false) {
+		if (start_on)
+			on();
+	}
+	~LogMakeDebugHdl() {
+		off();
+	}
+	void on() {
+		if (status) return;
+		status=true;
+		log_make_debug++;
+	}
+	void off_silent() {
+		if (!status) return;
+		status=false;
+		log_make_debug--;
+	}
+	void off() {
+		off_silent();
+	}
+};
+
 void log_spacer();
 void log_push();
 void log_pop();
diff --git a/kernel/register.cc b/kernel/register.cc
index 64956401f..71eb6b187 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -87,6 +87,7 @@ Pass::pre_post_exec_state_t Pass::pre_execute()
 void Pass::post_execute(Pass::pre_post_exec_state_t state)
 {
 	IdString::checkpoint();
+	log_suppressed();
 
 	int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
 	runtime_ns += time_ns;
diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc
index f5305cde9..cf3e46ace 100644
--- a/passes/cmds/trace.cc
+++ b/passes/cmds/trace.cc
@@ -94,4 +94,38 @@ struct TracePass : public Pass {
 	}
 } TracePass;
 
+struct DebugPass : public Pass {
+	DebugPass() : Pass("debug", "run command with debug log messages enabled") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    debug cmd\n");
+		log("\n");
+		log("Execute the specified command with debug log messages enabled\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// .. parse options ..
+			break;
+		}
+
+		log_force_debug++;
+
+		try {
+			std::vector<std::string> new_args(args.begin() + argidx, args.end());
+			Pass::call(design, new_args);
+		} catch (...) {
+			log_force_debug--;
+			throw;
+		}
+
+		log_force_debug--;
+	}
+} DebugPass;
+
 PRIVATE_NAMESPACE_END
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index c3b13acaf..c38e9df5e 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -137,7 +137,7 @@ void rmunused_module_cells(Module *module, bool verbose)
 
 	for (auto cell : unused) {
 		if (verbose)
-			log("  removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str());
+			log_debug("  removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str());
 		module->design->scratchpad_set_bool("opt.did_something", true);
 		module->remove(cell);
 		count_rm_cells++;
@@ -326,7 +326,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 	for (auto wire : maybe_del_wires)
 		if (!used_signals.check_any(RTLIL::SigSpec(wire))) {
 			if (check_public_name(wire->name) && verbose) {
-				log("  removing unused non-port wire %s.\n", wire->name.c_str());
+				log_debug("  removing unused non-port wire %s.\n", wire->name.c_str());
 			}
 			del_wires.insert(wire);
 			del_wires_count++;
@@ -336,7 +336,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 	count_rm_wires += del_wires.size();
 
 	if (verbose && del_wires_count > 0)
-		log("  removed %d unused temporary wires.\n", del_wires_count);
+		log_debug("  removed %d unused temporary wires.\n", del_wires_count);
 }
 
 bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose)
@@ -399,7 +399,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose)
 		}
 
 		if (verbose)
-			log("  removing redundant init attribute on %s.\n", log_id(wire));
+			log_debug("  removing redundant init attribute on %s.\n", log_id(wire));
 
 		wire->attributes.erase("\\init");
 		did_something = true;
@@ -426,7 +426,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
 		}
 	for (auto cell : delcells) {
 		if (verbose)
-			log("  removing buffer cell `%s': %s = %s\n", cell->name.c_str(),
+			log_debug("  removing buffer cell `%s': %s = %s\n", cell->name.c_str(),
 					log_signal(cell->getPort("\\Y")), log_signal(cell->getPort("\\A")));
 		module->remove(cell);
 	}
@@ -551,6 +551,7 @@ struct CleanPass : public Pass {
 			rmunused_module(module, purge_mode, false, false);
 		}
 
+		log_suppressed();
 		if (count_rm_cells > 0 || count_rm_wires > 0)
 			log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
 
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index a05db2a4f..af6d352af 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -67,7 +67,7 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
 		if (sig.size() == 0)
 			continue;
 
-		log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c));
+		log_debug("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c));
 		module->connect(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width)));
 		did_something = true;
 	}
@@ -78,7 +78,7 @@ void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell,
 	RTLIL::SigSpec Y = cell->getPort(out_port);
 	out_val.extend_u0(Y.size(), false);
 
-	log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
+	log_debug("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
 			cell->type.c_str(), cell->name.c_str(), info.c_str(),
 			module->name.c_str(), log_signal(Y), log_signal(out_val));
 	// log_cell(cell);
@@ -134,7 +134,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
 		if (GetSize(grouped_bits[i]) == GetSize(bits_y))
 			return false;
 
-	log("Replacing %s cell `%s' in module `%s' with cells using grouped bits:\n",
+	log_debug("Replacing %s cell `%s' in module `%s' with cells using grouped bits:\n",
 			log_id(cell->type), log_id(cell), log_id(module));
 
 	for (int i = 0; i < GRP_N; i++)
@@ -156,7 +156,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
 		}
 
 		if (cell->type.in("$and", "$or") && i == GRP_CONST_A) {
-			log("  Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
+			log_debug("  Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
 			module->connect(new_y, new_b);
 			module->connect(new_conn);
 			continue;
@@ -180,10 +180,10 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
 
 		module->connect(new_conn);
 
-		log("  New cell `%s': A=%s", log_id(c), log_signal(new_a));
+		log_debug("  New cell `%s': A=%s", log_id(c), log_signal(new_a));
 		if (b_name == "\\B")
-			log(", B=%s", log_signal(new_b));
-		log("\n");
+			log_debug(", B=%s", log_signal(new_b));
+		log_debug("\n");
 	}
 
 	cover_list("opt.opt_expr.fine.group", "$not", "$pos", "$and", "$or", "$xor", "$xnor", cell->type.str());
@@ -197,7 +197,7 @@ void handle_polarity_inv(Cell *cell, IdString port, IdString param, const SigMap
 {
 	SigSpec sig = assign_map(cell->getPort(port));
 	if (invert_map.count(sig)) {
-		log("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
+		log_debug("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
 				log_id(port), log_id(cell->type), log_id(cell), log_id(cell->module),
 				log_signal(sig), log_signal(invert_map.at(sig)));
 		cell->setPort(port, (invert_map.at(sig)));
@@ -226,7 +226,7 @@ void handle_clkpol_celltype_swap(Cell *cell, string type1, string type2, IdStrin
 	if (cell->type.in(type1, type2)) {
 		SigSpec sig = assign_map(cell->getPort(port));
 		if (invert_map.count(sig)) {
-			log("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
+			log_debug("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
 					log_id(port), log_id(cell->type), log_id(cell), log_id(cell->module),
 					log_signal(sig), log_signal(invert_map.at(sig)));
 			cell->setPort(port, (invert_map.at(sig)));
@@ -455,9 +455,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		{
 			if (cell->type == "$reduce_xnor") {
 				cover("opt.opt_expr.reduce_xnor_not");
-				log("Replacing %s cell `%s' in module `%s' with $not cell.\n",
+				log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n",
 						log_id(cell->type), log_id(cell->name), log_id(module));
 				cell->type = "$not";
+				did_something = true;
 			} else {
 				cover("opt.opt_expr.unary_buffer");
 				replace_cell(assign_map, module, cell, "unary_buffer", "\\Y", cell->getPort("\\A"));
@@ -488,7 +489,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 				if (GetSize(new_sig_a) < GetSize(sig_a)) {
 					cover_list("opt.opt_expr.fine.neutral_A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_and", "$reduce_bool", cell->type.str());
-					log("Replacing port A of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
+					log_debug("Replacing port A of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_sig_a));
 					cell->setPort("\\A", new_sig_a);
 					cell->parameters.at("\\A_WIDTH") = GetSize(new_sig_a);
@@ -511,7 +512,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 				if (GetSize(new_sig_b) < GetSize(sig_b)) {
 					cover_list("opt.opt_expr.fine.neutral_B", "$logic_and", "$logic_or", cell->type.str());
-					log("Replacing port B of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
+					log_debug("Replacing port B of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_sig_b));
 					cell->setPort("\\B", new_sig_b);
 					cell->parameters.at("\\B_WIDTH") = GetSize(new_sig_b);
@@ -537,7 +538,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 				if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) {
 					cover("opt.opt_expr.fine.$reduce_and");
-					log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
+					log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
 					cell->setPort("\\A", sig_a = new_a);
 					cell->parameters.at("\\A_WIDTH") = 1;
@@ -563,7 +564,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 				if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) {
 					cover_list("opt.opt_expr.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type.str());
-					log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
+					log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
 					cell->setPort("\\A", sig_a = new_a);
 					cell->parameters.at("\\A_WIDTH") = 1;
@@ -589,7 +590,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 				if (new_b != RTLIL::State::Sm && RTLIL::SigSpec(new_b) != sig_b) {
 					cover_list("opt.opt_expr.fine.B", "$logic_and", "$logic_or", cell->type.str());
-					log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
+					log_debug("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
 					cell->setPort("\\B", sig_b = new_b);
 					cell->parameters.at("\\B_WIDTH") = 1;
@@ -640,7 +641,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 		if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) {
 			cover_list("opt.opt_expr.invert.muxsel", "$_MUX_", "$mux", cell->type.str());
-			log("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module));
+			log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module));
 			RTLIL::SigSpec tmp = cell->getPort("\\A");
 			cell->setPort("\\A", cell->getPort("\\B"));
 			cell->setPort("\\B", tmp);
@@ -750,7 +751,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				ACTION_DO("\\Y", cell->getPort("\\A"));
 			if (input == State::S0 && !a.is_fully_undef()) {
 				cover("opt.opt_expr.action_" S__LINE__);
-				log("Replacing data input of %s cell `%s' in module `%s' with constant undef.\n",
+				log_debug("Replacing data input of %s cell `%s' in module `%s' with constant undef.\n",
 					cell->type.c_str(), cell->name.c_str(), module->name.c_str());
 				cell->setPort("\\A", SigSpec(State::Sx, GetSize(a)));
 				did_something = true;
@@ -822,7 +823,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 					ACTION_DO("\\Y", cell->getPort("\\A"));
 				} else {
 					cover_list("opt.opt_expr.eqneq.isnot", "$eq", "$ne", cell->type.str());
-					log("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
+					log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
 					cell->type = "$not";
 					cell->parameters.erase("\\B_WIDTH");
 					cell->parameters.erase("\\B_SIGNED");
@@ -837,7 +838,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				(assign_map(cell->getPort("\\A")).is_fully_zero() || assign_map(cell->getPort("\\B")).is_fully_zero()))
 		{
 			cover_list("opt.opt_expr.eqneq.cmpzero", "$eq", "$ne", cell->type.str());
-			log("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell),
+			log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell),
 					log_id(module), "$eq" ? "$logic_not" : "$reduce_bool");
 			cell->type = cell->type == "$eq" ? "$logic_not" : "$reduce_bool";
 			if (assign_map(cell->getPort("\\A")).is_fully_zero()) {
@@ -876,7 +877,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 			cover_list("opt.opt_expr.constshift", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", cell->type.str());
 
-			log("Replacing %s cell `%s' (B=%s, SHR=%d) in module `%s' with fixed wiring: %s\n",
+			log_debug("Replacing %s cell `%s' (B=%s, SHR=%d) in module `%s' with fixed wiring: %s\n",
 					log_id(cell->type), log_id(cell), log_signal(assign_map(cell->getPort("\\B"))), shift_bits, log_id(module), log_signal(sig_y));
 
 			module->connect(cell->getPort("\\Y"), sig_y);
@@ -939,7 +940,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				if (identity_wrt_b)
 					cover_list("opt.opt_expr.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
 
-				log("Replacing %s cell `%s' in module `%s' with identity for port %c.\n",
+				log_debug("Replacing %s cell `%s' in module `%s' with identity for port %c.\n",
 					cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
 
 				if (!identity_wrt_a) {
@@ -969,7 +970,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
 				cell->getPort("\\A") == RTLIL::SigSpec(1, 1) && cell->getPort("\\B") == RTLIL::SigSpec(0, 1)) {
 			cover_list("opt.opt_expr.mux_invert", "$mux", "$_MUX_", cell->type.str());
-			log("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
+			log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
 			cell->setPort("\\A", cell->getPort("\\S"));
 			cell->unsetPort("\\B");
 			cell->unsetPort("\\S");
@@ -988,7 +989,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1)) {
 			cover_list("opt.opt_expr.mux_and", "$mux", "$_MUX_", cell->type.str());
-			log("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
+			log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
 			cell->setPort("\\A", cell->getPort("\\S"));
 			cell->unsetPort("\\S");
 			if (cell->type == "$mux") {
@@ -1008,7 +1009,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) {
 			cover_list("opt.opt_expr.mux_or", "$mux", "$_MUX_", cell->type.str());
-			log("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
+			log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
 			cell->setPort("\\B", cell->getPort("\\S"));
 			cell->unsetPort("\\S");
 			if (cell->type == "$mux") {
@@ -1061,7 +1062,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 			if (cell->getPort("\\S").size() != new_s.size()) {
 				cover_list("opt.opt_expr.mux_reduce", "$mux", "$pmux", cell->type.str());
-				log("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
+				log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
 						GetSize(cell->getPort("\\S")) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module));
 				cell->setPort("\\A", new_a);
 				cell->setPort("\\B", new_b);
@@ -1179,7 +1180,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				{
 					cover("opt.opt_expr.mul_shift.zero");
 
-					log("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n",
+					log_debug("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n",
 							cell->name.c_str(), module->name.c_str());
 
 					module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
@@ -1197,7 +1198,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						else
 							cover("opt.opt_expr.mul_shift.unswapped");
 
-						log("Replacing multiply-by-%d cell `%s' in module `%s' with shift-by-%d.\n",
+						log_debug("Replacing multiply-by-%d cell `%s' in module `%s' with shift-by-%d.\n",
 								a_val, cell->name.c_str(), module->name.c_str(), i);
 
 						if (!swapped_ab) {
@@ -1237,7 +1238,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				{
 					cover("opt.opt_expr.divmod_zero");
 
-					log("Replacing divide-by-zero cell `%s' in module `%s' with undef-driver.\n",
+					log_debug("Replacing divide-by-zero cell `%s' in module `%s' with undef-driver.\n",
 							cell->name.c_str(), module->name.c_str());
 
 					module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(State::Sx, sig_y.size())));
@@ -1254,7 +1255,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						{
 							cover("opt.opt_expr.div_shift");
 
-							log("Replacing divide-by-%d cell `%s' in module `%s' with shift-by-%d.\n",
+							log_debug("Replacing divide-by-%d cell `%s' in module `%s' with shift-by-%d.\n",
 									b_val, cell->name.c_str(), module->name.c_str(), i);
 
 							std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(i, 6);
@@ -1272,7 +1273,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						{
 							cover("opt.opt_expr.mod_mask");
 
-							log("Replacing modulo-by-%d cell `%s' in module `%s' with bitmask.\n",
+							log_debug("Replacing modulo-by-%d cell `%s' in module `%s' with bitmask.\n",
 									b_val, cell->name.c_str(), module->name.c_str());
 
 							std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(State::S1, i);
@@ -1342,7 +1343,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				SigSpec y_sig = cell->getPort("\\Y");
 				Const y_value(cell->type.in("$eq", "$eqx") ? 0 : 1, GetSize(y_sig));
 
-				log("Replacing cell `%s' in module `%s' with constant driver %s.\n",
+				log_debug("Replacing cell `%s' in module `%s' with constant driver %s.\n",
 					log_id(cell), log_id(module), log_signal(y_value));
 
 				module->connect(y_sig, y_value);
@@ -1354,7 +1355,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 			if (redundant_bits)
 			{
-				log("Removed %d redundant input bits from %s cell `%s' in module `%s'.\n",
+				log_debug("Removed %d redundant input bits from %s cell `%s' in module `%s'.\n",
 						redundant_bits, log_id(cell->type), log_id(cell), log_id(module));
 
 				cell->setPort("\\A", sig_a);
@@ -1493,7 +1494,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 				if (replace || remove)
 				{
-					log("Replacing %s cell `%s' (implementing %s) with %s.\n",
+					log_debug("Replacing %s cell `%s' (implementing %s) with %s.\n",
 							log_id(cell->type), log_id(cell), condition.c_str(), replacement.c_str());
 					if (replace)
 						module->connect(cell->getPort("\\Y"), replace_sig);
@@ -1599,8 +1600,14 @@ struct OptExprPass : public Pass {
 
 		for (auto module : design->selected_modules())
 		{
-			if (undriven)
+			log("Optimizing module %s.\n", log_id(module));
+
+			if (undriven) {
+				did_something = false;
 				replace_undriven(design, module);
+				if (did_something)
+					design->scratchpad_set_bool("opt.did_something", true);
+			}
 
 			do {
 				do {
@@ -1610,7 +1617,11 @@ struct OptExprPass : public Pass {
 						design->scratchpad_set_bool("opt.did_something", true);
 				} while (did_something);
 				replace_const_cells(design, module, true, mux_undef, mux_bool, do_fine, keepdc, clkinv);
+				if (did_something)
+					design->scratchpad_set_bool("opt.did_something", true);
 			} while (did_something);
+
+			log_suppressed();
 		}
 
 		log_pop();
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index eedf88904..7567d4657 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -315,17 +315,17 @@ struct OptMergeWorker
 			{
 				if (sharemap.count(cell) > 0) {
 					did_something = true;
-					log("  Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
+					log_debug("  Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
 					for (auto &it : cell->connections()) {
 						if (cell->output(it.first)) {
 							RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first);
-							log("    Redirecting output %s: %s = %s\n", it.first.c_str(),
+							log_debug("    Redirecting output %s: %s = %s\n", it.first.c_str(),
 									log_signal(it.second), log_signal(other_sig));
 							module->connect(RTLIL::SigSig(it.second, other_sig));
 							assign_map.add(it.second, other_sig);
 						}
 					}
-					log("    Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
+					log_debug("    Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
 #ifdef USE_CELL_HASH_CACHE
 					cell_hash_cache.erase(cell);
 #endif
@@ -336,6 +336,8 @@ struct OptMergeWorker
 				}
 			}
 		}
+
+		log_suppressed();
 	}
 };
 
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 375697dc8..dbebf21e0 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -181,14 +181,14 @@ struct OptMuxtreeWorker
 
 		for (int mux_idx = 0; mux_idx < GetSize(root_muxes); mux_idx++)
 			if (root_muxes.at(mux_idx)) {
-				log("    Root of a mux tree: %s%s\n", log_id(mux2info[mux_idx].cell), root_enable_muxes.at(mux_idx) ? " (pure)" : "");
+				log_debug("    Root of a mux tree: %s%s\n", log_id(mux2info[mux_idx].cell), root_enable_muxes.at(mux_idx) ? " (pure)" : "");
 				root_mux_rerun.erase(mux_idx);
 				eval_root_mux(mux_idx);
 			}
 
 		while (!root_mux_rerun.empty()) {
 			int mux_idx = *root_mux_rerun.begin();
-			log("    Root of a mux tree: %s (rerun as non-pure)\n", log_id(mux2info[mux_idx].cell));
+			log_debug("    Root of a mux tree: %s (rerun as non-pure)\n", log_id(mux2info[mux_idx].cell));
 			log_assert(root_enable_muxes.at(mux_idx));
 			root_mux_rerun.erase(mux_idx);
 			eval_root_mux(mux_idx);
@@ -326,7 +326,7 @@ struct OptMuxtreeWorker
 				if (abort_count == 0) {
 					root_mux_rerun.insert(m);
 					root_enable_muxes.at(m) = true;
-					log("      Removing pure flag from root mux %s.\n", log_id(mux2info[m].cell));
+					log_debug("      Removing pure flag from root mux %s.\n", log_id(mux2info[m].cell));
 				} else
 					eval_mux(knowledge, m, false, do_enable_ports, abort_count - 1);
 			} else
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 1a4318460..ab0bd3b54 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -72,6 +72,8 @@ struct TechmapWorker
 	pool<IdString> flatten_done_list;
 	pool<Cell*> flatten_keep_list;
 
+	pool<string> log_msg_cache;
+
 	struct TechmapWireData {
 		RTLIL::Wire *wire;
 		RTLIL::SigSpec value;
@@ -390,6 +392,7 @@ struct TechmapWorker
 
 		bool log_continue = false;
 		bool did_something = false;
+		LogMakeDebugHdl mkdebug;
 
 		SigMap sigmap(module);
 
@@ -547,6 +550,7 @@ struct TechmapWorker
 								if (extmapper_name == "wrap") {
 									std::string cmd_string = tpl->attributes.at("\\techmap_wrap").decode_string();
 									log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
+									mkdebug.on();
 									Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
 									log_continue = true;
 								}
@@ -560,11 +564,21 @@ struct TechmapWorker
 								goto use_wrapper_tpl;
 							}
 
-							log("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
+							auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
+							if (!log_msg_cache.count(msg)) {
+								log_msg_cache.insert(msg);
+								log("%s\n", msg.c_str());
+							}
+							log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
 						}
 						else
 						{
-							log("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
+							auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
+							if (!log_msg_cache.count(msg)) {
+								log_msg_cache.insert(msg);
+								log("%s\n", msg.c_str());
+							}
+							log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
 
 							if (extmapper_name == "simplemap") {
 								if (simplemap_mappers.count(cell->type) == 0)
@@ -662,6 +676,7 @@ struct TechmapWorker
 						tpl = techmap_cache[key];
 					} else {
 						if (parameters.size() != 0) {
+							mkdebug.on();
 							derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end()));
 							tpl = map->module(derived_name);
 							log_continue = true;
@@ -831,6 +846,7 @@ struct TechmapWorker
 						if (log_continue) {
 							log_header(design, "Continuing TECHMAP pass.\n");
 							log_continue = false;
+							mkdebug.off();
 						}
 						while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
 					}
@@ -842,6 +858,7 @@ struct TechmapWorker
 				if (log_continue) {
 					log_header(design, "Continuing TECHMAP pass.\n");
 					log_continue = false;
+					mkdebug.off();
 				}
 
 				if (extern_mode && !in_recursion)
@@ -861,13 +878,18 @@ struct TechmapWorker
 						module_queue.insert(m);
 					}
 
-					log("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
+					log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
 					cell->type = m_name;
 					cell->parameters.clear();
 				}
 				else
 				{
-					log("%s %s.%s using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(tpl));
+					auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type));
+					if (!log_msg_cache.count(msg)) {
+						log_msg_cache.insert(msg);
+						log("%s\n", msg.c_str());
+					}
+					log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
 					techmap_module_worker(design, module, cell, tpl);
 					cell = NULL;
 				}
@@ -885,6 +907,7 @@ struct TechmapWorker
 		if (log_continue) {
 			log_header(design, "Continuing TECHMAP pass.\n");
 			log_continue = false;
+			mkdebug.off();
 		}
 
 		return did_something;
@@ -1085,7 +1108,7 @@ struct TechmapPass : public Pass {
 		if (map_files.empty()) {
 			std::istringstream f(stdcells_code);
 			Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
-		} else
+		} else {
 			for (auto &fn : map_files)
 				if (fn.substr(0, 1) == "%") {
 					if (!saved_designs.count(fn.substr(1))) {
@@ -1104,6 +1127,9 @@ struct TechmapPass : public Pass {
 						log_cmd_error("Can't open map file `%s'\n", fn.c_str());
 					Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
 				}
+		}
+
+		log_header(design, "Continuing TECHMAP pass.\n");
 
 		std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
 		for (auto &it : map->modules_) {
@@ -1211,6 +1237,7 @@ struct FlattenPass : public Pass {
 			}
 		}
 
+		log_suppressed();
 		log("No more expansions possible.\n");
 
 		if (top_mod != NULL)

From 4ad0ea5c3c325dc639829f6c6836353044585af5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 18:19:02 +0200
Subject: [PATCH 55/59] Determine correct signedness and expression width in
 for loop unrolling, fixes #370

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 76da5a97c..3e453bd7f 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1085,7 +1085,12 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
 		// eval 1st expression
 		AstNode *varbuf = init_ast->children[1]->clone();
-		while (varbuf->simplify(true, false, false, stage, 32, true, false)) { }
+		{
+			int expr_width_hint = -1;
+			bool expr_sign_hint = true;
+			varbuf->detectSignWidth(expr_width_hint, expr_sign_hint);
+			while (varbuf->simplify(true, false, false, stage, 32, true, false)) { }
+		}
 
 		if (varbuf->type != AST_CONSTANT)
 			log_file_error(filename, linenum, "Right hand side of 1st expression of generate for-loop is not constant!\n");
@@ -1107,7 +1112,12 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		{
 			// eval 2nd expression
 			AstNode *buf = while_ast->clone();
-			while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
+			{
+				int expr_width_hint = -1;
+				bool expr_sign_hint = true;
+				buf->detectSignWidth(expr_width_hint, expr_sign_hint);
+				while (buf->simplify(true, false, false, stage, expr_width_hint, expr_sign_hint, false)) { }
+			}
 
 			if (buf->type != AST_CONSTANT)
 				log_file_error(filename, linenum, "2nd expression of generate for-loop is not constant!\n");
@@ -1148,7 +1158,12 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
 			// eval 3rd expression
 			buf = next_ast->children[1]->clone();
-			while (buf->simplify(true, false, false, stage, 32, true, false)) { }
+			{
+				int expr_width_hint = -1;
+				bool expr_sign_hint = true;
+				buf->detectSignWidth(expr_width_hint, expr_sign_hint);
+				while (buf->simplify(true, false, false, stage, expr_width_hint, expr_sign_hint, true)) { }
+			}
 
 			if (buf->type != AST_CONSTANT)
 				log_file_error(filename, linenum, "Right hand side of 3rd expression of generate for-loop is not constant!\n");

From 0e0c80fac883a6f512a94aecdc3c915b8cacb562 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 22 Apr 2019 19:44:10 +0200
Subject: [PATCH 56/59] Add support for zero-width signals to Verilog back-end,
 fixes #948

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 855409d0b..9967482d6 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -187,6 +187,10 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 {
 	if (width < 0)
 		width = data.bits.size() - offset;
+	if (width == 0) {
+		f << "\"\"";
+		return;
+	}
 	if (nostr)
 		goto dump_hex;
 	if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
@@ -340,6 +344,10 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima
 
 void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 {
+	if (GetSize(sig) == 0) {
+		f << "\"\"";
+		return;
+	}
 	if (sig.is_chunk()) {
 		dump_sigchunk(f, sig.as_chunk());
 	} else {

From 2c6358ea25d595bf014a564860e3ffde7eddb2cb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 11:21:17 -0700
Subject: [PATCH 57/59] Remove kernel/cost.cc since master has refactored it

---
 Makefile       |  1 -
 kernel/cost.cc | 75 --------------------------------------------------
 2 files changed, 76 deletions(-)
 delete mode 100644 kernel/cost.cc

diff --git a/Makefile b/Makefile
index d9e01c865..249c1d0ee 100644
--- a/Makefile
+++ b/Makefile
@@ -471,7 +471,6 @@ $(eval $(call add_include_file,backends/ilang/ilang_backend.h))
 
 OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
 OBJS += kernel/cellaigs.o kernel/celledges.o
-OBJS += kernel/cost.o
 
 kernel/log.o: CXXFLAGS += -DYOSYS_SRC='"$(YOSYS_SRC)"'
 kernel/yosys.o: CXXFLAGS += -DYOSYS_DATDIR='"$(DATDIR)"'
diff --git a/kernel/cost.cc b/kernel/cost.cc
deleted file mode 100644
index 175f01e64..000000000
--- a/kernel/cost.cc
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/yosys.h"
-#include "kernel/cost.h"
-
-YOSYS_NAMESPACE_BEGIN
-
-int get_cell_cost(RTLIL::IdString type, const dict<RTLIL::IdString, RTLIL::Const> &parameters,
-		RTLIL::Design *design, dict<RTLIL::IdString, int> *mod_cost_cache)
-{
-	static dict<RTLIL::IdString, int> gate_cost = {
-		{ "$_BUF_",    1 },
-		{ "$_NOT_",    2 },
-		{ "$_AND_",    4 },
-		{ "$_NAND_",   4 },
-		{ "$_OR_",     4 },
-		{ "$_NOR_",    4 },
-		{ "$_ANDNOT_", 4 },
-		{ "$_ORNOT_",  4 },
-		{ "$_XOR_",    8 },
-		{ "$_XNOR_",   8 },
-		{ "$_AOI3_",   6 },
-		{ "$_OAI3_",   6 },
-		{ "$_AOI4_",   8 },
-		{ "$_OAI4_",   8 },
-		{ "$_MUX_",    4 }
-	};
-
-	if (gate_cost.count(type))
-		return gate_cost.at(type);
-
-	if (parameters.empty() && design && design->module(type))
-	{
-		RTLIL::Module *mod = design->module(type);
-
-		if (mod->attributes.count("\\cost"))
-			return mod->attributes.at("\\cost").as_int();
-
-		dict<RTLIL::IdString, int> local_mod_cost_cache;
-		if (mod_cost_cache == nullptr)
-			mod_cost_cache = &local_mod_cost_cache;
-
-		if (mod_cost_cache->count(mod->name))
-			return mod_cost_cache->at(mod->name);
-
-		int module_cost = 1;
-		for (auto c : mod->cells())
-			module_cost += get_cell_cost(c, mod_cost_cache);
-
-		(*mod_cost_cache)[mod->name] = module_cost;
-		return module_cost;
-	}
-
-	log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters));
-	return 1;
-}
-
-YOSYS_NAMESPACE_END

From b780c0a7de3b0f095099461af1434624d2af0c32 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 11:22:29 -0700
Subject: [PATCH 58/59] Allow POs to be PIs in XAIG

---
 backends/aiger/xaiger.cc | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index e93fd35f7..a881b1b88 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -161,12 +161,8 @@ struct XAigerWriter
 			}
 		}
 
-		for (auto bit : input_bits) {
-			if (!bit.wire->port_output)
-				undriven_bits.erase(bit);
-			// Erase POs that are also PIs
-			output_bits.erase(bit);
-		}
+		for (auto bit : input_bits)
+			undriven_bits.erase(bit);
 
 		for (auto bit : output_bits)
 			if (!bit.wire->port_input)
@@ -275,7 +271,8 @@ struct XAigerWriter
 						}
 					}
 				}
-				if (!abc_box_seen) abc_box_seen = inst_module->attributes.count("\\abc_box_id");
+				if (!abc_box_seen)
+					abc_box_seen = inst_module->attributes.count("\\abc_box_id");
 
 				ff_bits.emplace_back(d, q);
 				undriven_bits.erase(q);

From eaf3c247729365cec776e147f380ce59f7dccd4d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 11:54:19 -0700
Subject: [PATCH 59/59] Temporarily remove 'r' extension

---
 backends/aiger/xaiger.cc      | 84 +++--------------------------------
 frontends/aiger/aigerparse.cc | 18 --------
 2 files changed, 7 insertions(+), 95 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index a881b1b88..d6438a297 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -50,7 +50,6 @@ struct XAigerWriter
 	dict<SigBit, pair<SigBit, SigBit>> and_map;
 	//pool<SigBit> initstate_bits;
 	vector<std::pair<SigBit,int>> ci_bits, co_bits;
-	vector<std::pair<SigBit,SigBit>> ff_bits;
 
 	vector<pair<int, int>> aig_gates;
 	vector<int> aig_latchin, aig_latchinit, aig_outputs;
@@ -175,7 +174,6 @@ struct XAigerWriter
 		for (auto cell : module->cells())
 		{
 			RTLIL::Module* inst_module = module->design->module(cell->type);
-			bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
 			bool known_type = yosys_celltypes.cell_known(cell->type);
 
 			if (!holes_mode) {
@@ -252,32 +250,7 @@ struct XAigerWriter
 			//	continue;
 			//}
 
-			if (inst_flop) {
-				SigBit d, q;
-				for (const auto &c : cell->connections()) {
-					for (auto b : c.second.bits()) {
-						auto is_input = cell->input(c.first);
-						auto is_output = cell->output(c.first);
-						log_assert(is_input || is_output);
-						if (is_input && inst_module->wire(c.first)->attributes.count("\\abc_flop_d")) {
-							SigBit I = sigmap(b);
-							if (I != b)
-								alias_map[b] = I;
-							d = b;
-						}
-						if (is_output && inst_module->wire(c.first)->attributes.count("\\abc_flop_q")) {
-						    SigBit O = sigmap(b);
-							q = O;
-						}
-					}
-				}
-				if (!abc_box_seen)
-					abc_box_seen = inst_module->attributes.count("\\abc_box_id");
-
-				ff_bits.emplace_back(d, q);
-				undriven_bits.erase(q);
-			}
-			else if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
+			if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
 				abc_box_seen = true;
 			}
 			else {
@@ -420,20 +393,10 @@ struct XAigerWriter
 			aig_map[bit] = 2*aig_m;
 		}
 
-		for (auto &f : ff_bits) {
-			auto bit = f.second;
-			aig_m++, aig_i++;
-			aig_map[bit] = 2*aig_m;
-		}
-
-		dict<SigBit, int> ff_aig_map;
 		for (auto &c : ci_bits) {
 			aig_m++, aig_i++;
 			c.second = 2*aig_m;
-			auto r = aig_map.insert(std::make_pair(c.first, c.second));
-			if (!r.second) {
-				ff_aig_map[c.first] = c.second;
-			}
+            aig_map[c.first] = c.second;
 		}
 
 		if (imode && input_bits.empty()) {
@@ -508,11 +471,6 @@ struct XAigerWriter
 			aig_outputs.push_back(bit2aig(bit));
 		}
 
-		for (auto &f : ff_bits) {
-			aig_o++;
-			aig_outputs.push_back(ff_aig_map.at(f.second));
-		}
-
 		if (omode && output_bits.empty()) {
 			aig_o++;
 			aig_outputs.push_back(0);
@@ -670,7 +628,7 @@ struct XAigerWriter
 
 		f << "c";
 
-		if (!box_list.empty() || !ff_bits.empty()) {
+		if (!box_list.empty()) {
 			std::stringstream h_buffer;
 			auto write_h_buffer = [&h_buffer](int i32) {
 				// TODO: Don't assume we're on little endian
@@ -685,10 +643,10 @@ struct XAigerWriter
 			if (omode && num_outputs == 0)
 				num_outputs = 1;
 			write_h_buffer(1);
-			write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
-			write_h_buffer(num_outputs + ff_bits.size() + co_bits.size());
-			write_h_buffer(input_bits.size() + ff_bits.size());
-			write_h_buffer(num_outputs + ff_bits.size());
+			write_h_buffer(input_bits.size() + ci_bits.size());
+			write_h_buffer(num_outputs + co_bits.size());
+			write_h_buffer(input_bits.size());
+			write_h_buffer(num_outputs);
 			write_h_buffer(box_list.size());
 
 			RTLIL::Module *holes_module = nullptr;
@@ -741,34 +699,6 @@ struct XAigerWriter
 			f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
 			f.write(buffer_str.data(), buffer_str.size());
 
-			if (!ff_bits.empty()) {
-				std::stringstream r_buffer;
-				auto write_r_buffer = [&r_buffer](int i32) {
-					// TODO: Don't assume we're on little endian
-#ifdef _WIN32
-					int i32_be = _byteswap_ulong(i32);
-#else
-					int i32_be = __builtin_bswap32(i32);
-#endif
-					r_buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
-				};
-				write_r_buffer(ff_bits.size());
-				int mergeability_class = 1;
-				for (auto cell : ff_bits)
-					write_r_buffer(mergeability_class++);
-
-				f << "r";
-				std::string buffer_str = r_buffer.str();
-				// TODO: Don't assume we're on little endian
-#ifdef _WIN32
-				int buffer_size_be = _byteswap_ulong(buffer_str.size());
-#else
-				int buffer_size_be = __builtin_bswap32(buffer_str.size());
-#endif
-				f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
-				f.write(buffer_str.data(), buffer_str.size());
-			}
-
 			if (holes_module) {
 				holes_module->fixup_ports();
 
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 4e3f5e7c9..3fa6f5c2d 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -360,24 +360,6 @@ void AigerReader::parse_xaiger()
                     module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
                 }
             }
-            else if (c == 'r') {
-                uint32_t dataSize = parse_xaiger_literal(f);
-                uint32_t flopNum = parse_xaiger_literal(f);
-                f.ignore(flopNum * sizeof(uint32_t));
-                log_assert(inputs.size() >= flopNum);
-                for (auto it = inputs.end() - flopNum; it != inputs.end(); ++it) {
-                    log_assert((*it)->port_input);
-                    (*it)->port_input = false;
-                }
-                inputs.erase(inputs.end() - flopNum, inputs.end());
-                log_assert(outputs.size() >= flopNum);
-                for (auto it = outputs.end() - flopNum; it != outputs.end(); ++it) {
-                    log_assert((*it)->port_output);
-                    (*it)->port_output = false;
-                }
-                outputs.erase(outputs.end() - flopNum, outputs.end());
-                module->fixup_ports();
-            }
             else if (c == 'n') {
                parse_xaiger_literal(f);
                f >> s;