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Add '-nosrl' option to synth_xilinx

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This commit is contained in:
Eddie Hung 2019-03-21 15:04:44 -07:00
parent 5597270b9e
commit 4cc6b3e942
1 changed files with 16 additions and 6 deletions
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22
techlibs/xilinx/synth_xilinx.cc
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@ -64,10 +64,13 @@ struct SynthXilinxPass : public Pass
log(" (this feature is experimental and incomplete)\n"); log(" (this feature is experimental and incomplete)\n");
log("\n"); log("\n");
log(" -nobram\n"); log(" -nobram\n");
log(" disable infering of block rams\n"); log(" disable inference of block rams\n");
log("\n"); log("\n");
log(" -nodram\n"); log(" -nodram\n");
log(" disable infering of distributed rams\n"); log(" disable inference of distributed rams\n");
log("\n");
log(" -nobram\n");
log(" disable inference of shift registers\n");
log("\n"); log("\n");
log(" -run <from_label>:<to_label>\n"); log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n"); log(" only run the commands between the labels (see below). an empty\n");
@ -110,8 +113,8 @@ struct SynthXilinxPass : public Pass
log(" dffsr2dff\n"); log(" dffsr2dff\n");
log(" dff2dffe\n"); log(" dff2dffe\n");
log(" opt -full\n"); log(" opt -full\n");
log(" simplemap t:$dff*\n"); log(" simplemap t:$dff* (only without -nosrl)\n");
log(" shregmap -tech xilinx\n"); log(" shregmap -tech xilinx (only without -nosrl)\n");
log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
log(" opt -fast\n"); log(" opt -fast\n");
log("\n"); log("\n");
@ -149,6 +152,7 @@ struct SynthXilinxPass : public Pass
bool vpr = false; bool vpr = false;
bool nobram = false; bool nobram = false;
bool nodram = false; bool nodram = false;
bool nosrl = false;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
@ -193,6 +197,10 @@ struct SynthXilinxPass : public Pass
nodram = true; nodram = true;
continue; continue;
} }
if (args[argidx] == "-nosrl") {
nosrl = true;
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
@ -257,8 +265,10 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "dff2dffe"); Pass::call(design, "dff2dffe");
Pass::call(design, "opt -full"); Pass::call(design, "opt -full");
Pass::call(design, "simplemap t:$dff*"); if (!nosrl) {
Pass::call(design, "shregmap -tech xilinx"); Pass::call(design, "simplemap t:$dff*");
Pass::call(design, "shregmap -tech xilinx");
}
if (vpr) { if (vpr) {
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");