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quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged

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Emil J. Tywoniak 2025-03-10 17:12:31 +01:00 • committed by Martin Povišer
parent fb3ad314ba
commit 4cbc92f50f
8 changed files with 157 additions and 20 deletions
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5
techlibs/quicklogic/qlf_k6n10f/dspv1_sim.v
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@ -4195,8 +4195,7 @@ module dsp_t1_20x18x64_cfg_ports (
input wire [ 5:0] shift_right_i,
input wire round_i,
input wire subtract_i,
input wire register_inputs_i,
input wire f_mode_i
input wire register_inputs_i
);
parameter [19:0] COEFF_0 = 20'd0;
@ -4212,7 +4211,7 @@ module dsp_t1_20x18x64_cfg_ports (
.z(z_o),
.dly_b(dly_b_o),
.f_mode(f_mode_i), // 20x18x64 DSP
.f_mode(1'b0), // 20x18x64 DSP
.acc_fir(acc_fir_i),
.feedback(feedback_i),