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quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged

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This commit is contained in:
Emil J. Tywoniak 2025-03-10 17:12:31 +01:00 • committed by Martin Povišer
parent fb3ad314ba
commit 4cbc92f50f
8 changed files with 157 additions and 20 deletions
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62
techlibs/quicklogic/qlf_k6n10f/dspv1_final_map.v
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@ -14,7 +14,7 @@
//
// SPDX-License-Identifier: Apache-2.0
module dsp_t1_20x18x64_cfg_ports (
module dsp_t1_20x18x64_cfg_ports_fracturable (
input [19:0] a_i,
input [17:0] b_i,
input [ 5:0] acc_fir_i,
@ -60,7 +60,7 @@ module dsp_t1_20x18x64_cfg_ports (
.unsigned_a (unsigned_a_i),
.unsigned_b (unsigned_b_i),
.f_mode (f_mode_i), // No fracturation
.f_mode (f_mode_i),
.output_select (output_select_i),
.saturate_enable (saturate_enable_i),
.shift_right (shift_right_i),
@ -71,6 +71,62 @@ module dsp_t1_20x18x64_cfg_ports (
endmodule
module dsp_t1_20x18x64_cfg_ports (
input [19:0] a_i,
input [17:0] b_i,
input [ 5:0] acc_fir_i,
output [37:0] z_o,
output [17:0] dly_b_o,
input clock_i,
input reset_i,
input [2:0] feedback_i,
input load_acc_i,
input unsigned_a_i,
input unsigned_b_i,
input [2:0] output_select_i,
input saturate_enable_i,
input [5:0] shift_right_i,
input round_i,
input subtract_i,
input register_inputs_i
);
parameter [19:0] COEFF_0 = 20'd0;
parameter [19:0] COEFF_1 = 20'd0;
parameter [19:0] COEFF_2 = 20'd0;
parameter [19:0] COEFF_3 = 20'd0;
dsp_t1_20x18x64_cfg_ports_fracturable # (
.COEFF_0 (COEFF_0),
.COEFF_1 (COEFF_1),
.COEFF_2 (COEFF_2),
.COEFF_3 (COEFF_3)
) _TECHMAP_REPLACE_ (
.a_i (a_i),
.b_i (b_i),
.acc_fir_i (acc_fir_i),
.z_o (z_o),
.dly_b_o (dly_b_o),
.clock_i (clock_i),
.reset_i (reset_i),
.feedback_i (feedback_i),
.load_acc_i (load_acc_i),
.unsigned_a_i (unsigned_a_i),
.unsigned_b_i (unsigned_b_i),
.output_select_i (output_select_i),
.saturate_enable_i (saturate_enable_i),
.shift_right_i (shift_right_i),
.round_i (round_i),
.subtract_i (subtract_i),
.register_inputs_i (register_inputs_i),
.f_mode_i (1'b0)
);
endmodule
module dsp_t1_10x9x32_cfg_ports (
input [ 9:0] a_i,
input [ 8:0] b_i,
@ -123,7 +179,7 @@ module dsp_t1_10x9x32_cfg_ports (
.unsigned_a (unsigned_a_i),
.unsigned_b (unsigned_b_i),
.f_mode (1'b1), // Enable fractuation, Use the lower half
.f_mode (1'b0),
.output_select (output_select_i),
.saturate_enable (saturate_enable_i),
.shift_right (shift_right_i),

5
techlibs/quicklogic/qlf_k6n10f/dspv1_sim.v
View file

@ -4195,8 +4195,7 @@ module dsp_t1_20x18x64_cfg_ports (
input wire [ 5:0] shift_right_i,
input wire round_i,
input wire subtract_i,
input wire register_inputs_i,
input wire f_mode_i
input wire register_inputs_i
);
parameter [19:0] COEFF_0 = 20'd0;
@ -4212,7 +4211,7 @@ module dsp_t1_20x18x64_cfg_ports (
.z(z_o),
.dly_b(dly_b_o),
.f_mode(f_mode_i), // 20x18x64 DSP
.f_mode(1'b0), // 20x18x64 DSP
.acc_fir(acc_fir_i),
.feedback(feedback_i),

80
techlibs/quicklogic/qlf_k6n10f/dspv1_sim_extra.v Normal file
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@ -0,0 +1,80 @@
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`timescale 1ps/1ps
`default_nettype none
// dsp_t1_20x18x64_cfg_ports but with input wire f_mode_i
// This is a yosys-specific extension beyond the vendor-provided model
module dsp_t1_20x18x64_cfg_ports_fracturable (
input wire [19:0] a_i,
input wire [17:0] b_i,
input wire [ 5:0] acc_fir_i,
output wire [37:0] z_o,
output wire [17:0] dly_b_o,
(* clkbuf_sink *)
input wire clock_i,
input wire reset_i,
input wire [ 2:0] feedback_i,
input wire load_acc_i,
input wire unsigned_a_i,
input wire unsigned_b_i,
input wire [ 2:0] output_select_i,
input wire saturate_enable_i,
input wire [ 5:0] shift_right_i,
input wire round_i,
input wire subtract_i,
input wire register_inputs_i,
input wire f_mode_i
);
parameter [19:0] COEFF_0 = 20'd0;
parameter [19:0] COEFF_1 = 20'd0;
parameter [19:0] COEFF_2 = 20'd0;
parameter [19:0] COEFF_3 = 20'd0;
QL_DSP2 #(
.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
) dsp (
.a(a_i),
.b(b_i),
.z(z_o),
.dly_b(dly_b_o),
.f_mode(f_mode_i), // 20x18x64 DSP
.acc_fir(acc_fir_i),
.feedback(feedback_i),
.load_acc(load_acc_i),
.unsigned_a(unsigned_a_i),
.unsigned_b(unsigned_b_i),
.clk(clock_i),
.reset(reset_i),
.saturate_enable(saturate_enable_i),
.output_select(output_select_i),
.round(round_i),
.shift_right(shift_right_i),
.subtract(subtract_i),
.register_inputs(register_inputs_i)
);
endmodule