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Create synth_analogdevices
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Lofty
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504
techlibs/analogdevices/synth_analogdevices.cc
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504
techlibs/analogdevices/synth_analogdevices.cc
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* (C) 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthAnalogDevicesPass : public ScriptPass
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{
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SynthAnalogDevicesPass() : ScriptPass("synth_analogdevices", "synthesis for Analog Devices FPGAs") { }
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void on_register() override
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{
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RTLIL::constpad["synth_analogdevices.abc9.W"] = "300"; // Number with which ABC will map a 6-input gate
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// to one LUT6 (instead of a LUT5 + LUT2)
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}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_analogdevices [options]\n");
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log("\n");
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log("This command runs synthesis for Analog Devices FPGAs. This command does not operate on\n");
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log("partly selected designs.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module\n");
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log("\n");
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log(" -edif <file>\n");
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log(" write the design to the specified edif file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use block RAM cells in output netlist\n");
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log("\n");
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log(" -nolutram\n");
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log(" do not use distributed RAM cells in output netlist\n");
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log("\n");
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log(" -nosrl\n");
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log(" do not use distributed SRL cells in output netlist\n");
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log("\n");
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log(" -nocarry\n");
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log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
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log("\n");
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log(" -nowidelut\n");
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log(" do not use MUXF[7-8] resources to implement LUTs larger than native for\n");
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log(" the target\n");
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log("\n");
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log(" -nodsp\n");
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log(" do not use DSP48*s to implement multipliers and associated logic\n");
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log("\n");
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log(" -noiopad\n");
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log(" disable I/O buffer insertion (useful for hierarchical or \n");
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log(" out-of-context flows)\n");
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log("\n");
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log(" -noclkbuf\n");
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log(" disable automatic clock buffer insertion\n");
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log("\n");
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log(" -widemux <int>\n");
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log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at\n");
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log(" or above this number of inputs (minimum value 2, recommended value >= 5)\n");
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log(" default: 0 (no inference)\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -dff\n");
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log(" run 'abc'/'abc9' with -dff option\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with '-D 1' option to enable flip-flop retiming.\n");
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log(" implies -dff.\n");
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log("\n");
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log(" -noabc9\n");
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log(" disable use of new ABC9 flow\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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std::string top_opt, edif_file, json_file;
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bool flatten, retime, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp;
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bool abc9, dff;
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bool flatten_before_abc;
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int widemux;
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int widelut_size;
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void clear_flags() override
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{
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top_opt = "-auto-top";
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edif_file.clear();
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flatten = true;
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retime = false;
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noiopad = false;
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noclkbuf = false;
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nocarry = false;
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nobram = false;
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nolutram = false;
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nosrl = false;
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nocarry = false;
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nowidelut = false;
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nodsp = false;
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abc9 = true;
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dff = false;
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flatten_before_abc = false;
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widemux = 0;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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std::string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-edif" && argidx+1 < args.size()) {
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edif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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if (args[argidx] == "-flatten_before_abc") {
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flatten_before_abc = true;
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continue;
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}
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if (args[argidx] == "-retime") {
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dff = true;
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retime = true;
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continue;
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}
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if (args[argidx] == "-nocarry") {
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nocarry = true;
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continue;
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}
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if (args[argidx] == "-nowidelut") {
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nowidelut = true;
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continue;
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}
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if (args[argidx] == "-iopad") {
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continue;
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}
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if (args[argidx] == "-noiopad") {
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noiopad = true;
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continue;
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}
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if (args[argidx] == "-noclkbuf") {
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noclkbuf = true;
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continue;
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}
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if (args[argidx] == "-nocarry") {
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nocarry = true;
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continue;
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}
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if (args[argidx] == "-nobram") {
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nobram = true;
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continue;
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}
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if (args[argidx] == "-nolutram") {
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nolutram = true;
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continue;
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}
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if (args[argidx] == "-nosrl") {
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nosrl = true;
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continue;
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}
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if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
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widemux = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-noabc9") {
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abc9 = false;
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continue;
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}
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if (args[argidx] == "-nodsp") {
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nodsp = true;
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continue;
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}
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if (args[argidx] == "-dff") {
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dff = true;
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continue;
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}
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if (args[argidx] == "-json" && argidx+1 < args.size()) {
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json_file = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (widemux != 0 && widemux < 2)
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log_cmd_error("-widemux value must be 0 or >= 2.\n");
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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if (abc9 && retime)
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log_cmd_error("-retime option not currently compatible with -abc9!\n");
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log_header(design, "Executing SYNTH_ANALOGDEVICES pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() override
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{
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if (check_label("begin")) {
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std::string read_args;
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read_args += " -lib -specify +/analogdevices/cells_sim.v";
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run("read_verilog" + read_args);
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run("read_verilog -lib +/analogdevices/cells_xtra.v");
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run(stringf("hierarchy -check %s", top_opt.c_str()));
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}
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if (check_label("prepare")) {
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run("proc");
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if (flatten || help_mode)
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run("flatten", "(with '-flatten')");
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if (active_design)
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active_design->scratchpad_unset("tribuf.added_something");
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run("tribuf -logic");
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if (noiopad && active_design && active_design->scratchpad_get_bool("tribuf.added_something"))
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log_error("Tristate buffers are unsupported without the '-iopad' option.\n");
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run("deminout");
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run("opt_expr");
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run("opt_clean");
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run("check");
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run("opt -nodffe -nosdff");
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run("fsm");
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run("opt");
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if (help_mode)
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run("wreduce [-keepdc]", "(option for '-widemux')");
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else
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run("wreduce" + std::string(widemux > 0 ? " -keepdc" : ""));
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run("peepopt");
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run("opt_clean");
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if (widemux > 0 || help_mode)
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run("muxpack", " ('-widemux' only)");
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// xilinx_srl looks for $shiftx cells for identifying variable-length
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// shift registers, so attempt to convert $pmux-es to this
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// Also: wide multiplexer inference benefits from this too
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if (!(nosrl && widemux == 0) || help_mode) {
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run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
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run("clean", " (skip if '-nosrl' and '-widemux=0')");
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}
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}
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if (check_label("map_dsp", "(skip if '-nodsp')")) {
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if (!nodsp || help_mode) {
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run("memory_dff"); // xilinx_dsp will merge registers, reserve memory port registers first
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// NB: Xilinx multipliers are signed only
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if (help_mode)
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run("techmap -map +/mul2dsp.v -map +/analogdevices/{family}_dsp_map.v {options}");
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run("techmap -map +/mul2dsp.v -map +/analogdevices/dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 "
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"-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally
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// limited to 18x18 in order to take
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// advantage of the (PCOUT << 17) -> PCIN
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// dedicated cascade chain capability
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"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
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"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
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"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
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run("select a:mul2dsp");
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run("setattr -unset mul2dsp");
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run("opt_expr -fine");
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run("wreduce");
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run("select -clear");
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if (help_mode)
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run("xilinx_dsp -family <family>");
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else
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run("xilinx_dsp -family xc7");
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run("chtype -set $mul t:$__soft_mul");
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}
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}
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if (check_label("coarse")) {
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run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=6");
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run("alumacc");
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run("share");
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run("opt");
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run("memory -nomap");
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run("opt_clean");
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}
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if (check_label("map_memory")) {
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std::string params = "";
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std::string lutrams_map = "+/analogdevices/lutrams_<family>_map.v";
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std::string brams_map = "+/analogdevices/brams_<family>_map.v";
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if (help_mode) {
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params = " [...]";
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} else {
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params += " -logic-cost-rom 0.015625";
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params += " -lib +/analogdevices/lutrams.txt";
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lutrams_map = "+/analogdevices/lutrams_map.v";
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params += " -lib +/analogdevices/brams.txt";
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params += " -D HAS_SIZE_36";
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params += " -D HAS_CASCADE";
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params += " -D HAS_CONFLICT_BUG";
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params += " -D HAS_MIXWIDTH_SDP";
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brams_map = "+/analogdevices/brams_map.v";
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if (nolutram)
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params += " -no-auto-distributed";
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if (nobram)
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params += " -no-auto-block";
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}
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run("memory_libmap" + params);
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run("techmap -map " + lutrams_map);
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run("techmap -map " + brams_map);
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}
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if (check_label("map_ffram")) {
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if (widemux > 0) {
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run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
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// performs less efficiently
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} else {
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run("opt -fast -full");
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}
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run("memory_map");
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}
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if (check_label("fine")) {
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if (help_mode) {
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run("simplemap t:$mux", "('-widemux' only)");
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run("muxcover <internal options>", "('-widemux' only)");
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} else if (widemux > 0) {
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run("simplemap t:$mux");
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constexpr int cost_mux2 = 100;
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std::string muxcover_args = stringf(" -nodecode -mux2=%d", cost_mux2);
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switch (widemux) {
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case 2: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2+1, cost_mux2+2, cost_mux2+3); break;
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case 3:
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case 4: muxcover_args += stringf(" -mux4=%d -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-2, cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
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case 5:
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case 6:
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case 7:
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case 8: muxcover_args += stringf(" -mux8=%d -mux16=%d", cost_mux2*(widemux-1)-1, cost_mux2*(widemux-1)); break;
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case 9:
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case 10:
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case 11:
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case 12:
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case 13:
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case 14:
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case 15:
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default: muxcover_args += stringf(" -mux16=%d", cost_mux2*(widemux-1)-1); break;
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}
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run("muxcover " + muxcover_args);
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}
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run("opt -full");
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if (!nosrl || help_mode)
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run("xilinx_srl -variable -minlen 3", "(skip if '-nosrl')");
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std::string techmap_args = " -map +/techmap.v -D LUT_SIZE=6";
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if (help_mode)
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techmap_args += " [-map +/analogdevices/mux_map.v]";
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else if (widemux > 0)
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techmap_args += stringf(" -D MIN_MUX_INPUTS=%d -map +/analogdevices/mux_map.v", widemux);
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if (!nocarry) {
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techmap_args += " -map +/analogdevices/arith_map.v";
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}
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run("techmap " + techmap_args);
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run("opt -fast");
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}
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if (check_label("map_cells")) {
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// Needs to be done before logic optimization, so that inverters (inserted
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// here because of negative-polarity output enable) are handled.
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if (help_mode || !noiopad)
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run("iopadmap -bits -outpad OUTBUF I:O -inpad INBUF O:I -toutpad OBUFT ~T:I:O -tinoutpad IOBUF ~T:O:I:IO A:top", "(skip if '-noiopad')");
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std::string techmap_args = "-map +/techmap.v -map +/analogdevices/cells_map.v";
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if (widemux > 0)
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techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
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run("techmap " + techmap_args);
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run("clean");
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}
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if (check_label("map_ffs")) {
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run("dfflegalize -cell $_DFFE_?P?P_ 01 -cell $_SDFFE_?P?P_ 01");
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if (abc9 || help_mode) {
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if (dff || help_mode)
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run("zinit -all w:* t:$_SDFFE_*", "('-dff' only)");
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run("techmap -map +/analogdevices/ff_map.v", "('-abc9' only)");
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}
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}
|
||||
|
||||
if (check_label("map_luts")) {
|
||||
run("opt_expr -mux_undef -noclkinv");
|
||||
if (flatten_before_abc)
|
||||
run("flatten");
|
||||
if (help_mode)
|
||||
run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
|
||||
else if (abc9) {
|
||||
run("read_verilog -icells -lib -specify +/analogdevices/abc9_model.v");
|
||||
std::string abc9_opts;
|
||||
std::string k = "synth_analogdevices.abc9.W";
|
||||
if (active_design && active_design->scratchpad.count(k))
|
||||
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
|
||||
else {
|
||||
abc9_opts += stringf(" -W %s", RTLIL::constpad.at("synth_analogdevices.abc9.W").c_str());
|
||||
}
|
||||
if (nowidelut)
|
||||
abc9_opts += stringf(" -maxlut 6");
|
||||
if (dff)
|
||||
abc9_opts += " -dff";
|
||||
run("abc9" + abc9_opts);
|
||||
}
|
||||
else {
|
||||
std::string abc_opts;
|
||||
if (nowidelut)
|
||||
abc_opts += " -luts 2:2,3,6:5";
|
||||
else
|
||||
abc_opts += " -luts 2:2,3,6:5,10,20";
|
||||
if (dff)
|
||||
abc_opts += " -dff";
|
||||
if (retime)
|
||||
abc_opts += " -D 1";
|
||||
run("abc" + abc_opts);
|
||||
}
|
||||
run("clean");
|
||||
|
||||
if (help_mode || !abc9)
|
||||
run("techmap -map +/analogdevices/ff_map.v", "(only if not '-abc9')");
|
||||
// This shregmap call infers fixed length shift registers after abc
|
||||
// has performed any necessary retiming
|
||||
if (!nosrl || help_mode)
|
||||
run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
|
||||
std::string techmap_args = "-map +/analogdevices/lut_map.v -map +/analogdevices/cells_map.v";
|
||||
techmap_args += " -D LUT_WIDTH=6";
|
||||
run("techmap " + techmap_args);
|
||||
run("xilinx_dffopt");
|
||||
run("opt_lut_ins -tech xilinx");
|
||||
}
|
||||
|
||||
if (check_label("finalize")) {
|
||||
if (help_mode || !noclkbuf)
|
||||
run("clkbufmap -buf BUFG O:I", "(skip if '-noclkbuf')");
|
||||
run("clean");
|
||||
}
|
||||
|
||||
if (check_label("check")) {
|
||||
run("hierarchy -check");
|
||||
run("stat -tech xilinx");
|
||||
run("check -noinit");
|
||||
run("blackbox =A:whitebox");
|
||||
}
|
||||
|
||||
if (check_label("edif")) {
|
||||
if (!edif_file.empty() || help_mode)
|
||||
run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
|
||||
}
|
||||
}
|
||||
} SynthAnalogDevicesPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
Loading…
Add table
Add a link
Reference in a new issue