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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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10
passes/techmap/techmap.cc
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@ -116,7 +116,7 @@ struct TechmapWorker
std::string orig_cell_name;
if (!flatten_mode)
for (auto &it : tpl->cells)
for (auto &it : tpl->cells_)
if (it.first == "\\_TECHMAP_REPLACE_") {
orig_cell_name = cell->name;
module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name);
@ -180,7 +180,7 @@ struct TechmapWorker
}
}
for (auto &it : tpl->cells)
for (auto &it : tpl->cells_)
{
RTLIL::IdString c_name = it.second->name;
@ -224,15 +224,15 @@ struct TechmapWorker
std::vector<std::string> cell_names;
SigMap sigmap(module);
for (auto &cell_it : module->cells)
for (auto &cell_it : module->cells_)
cell_names.push_back(cell_it.first);
for (auto &cell_name : cell_names)
{
if (module->cells.count(cell_name) == 0)
if (module->cells_.count(cell_name) == 0)
continue;
RTLIL::Cell *cell = module->cells[cell_name];
RTLIL::Cell *cell = module->cells_[cell_name];
if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
continue;