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Refactoring: Renamed RTLIL::Module::cells to cells_
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61 changed files with 152 additions and 152 deletions
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@ -182,7 +182,7 @@ namespace
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std::map<std::pair<RTLIL::Wire*, int>, int> sig_use_count;
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if (max_fanout > 0)
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for (auto &cell_it : mod->cells)
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for (auto &cell_it : mod->cells_)
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{
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RTLIL::Cell *cell = cell_it.second;
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if (!sel || sel->selected(mod, cell))
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@ -196,7 +196,7 @@ namespace
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}
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// create graph nodes from cells
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for (auto &cell_it : mod->cells)
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for (auto &cell_it : mod->cells_)
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{
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RTLIL::Cell *cell = cell_it.second;
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if (sel && !sel->selected(mod, cell))
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@ -253,7 +253,7 @@ namespace
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}
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// mark external signals (used in non-selected cells)
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for (auto &cell_it : mod->cells)
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for (auto &cell_it : mod->cells_)
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{
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RTLIL::Cell *cell = cell_it.second;
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if (sel && !sel->selected(mod, cell))
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