mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 13:18:56 +00:00
Code Activity

Refactoring: Renamed RTLIL::Module::cells to cells_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/techmap/dfflibmap.cc
View file

@ -388,7 +388,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
log("Mapping DFF cells in module `%s':\n", module->name.c_str());
std::vector<RTLIL::Cell*> cell_list;
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0)
cell_list.push_back(it.second);
}