mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-31 00:13:18 +00:00
Code Activity

Refactoring: Renamed RTLIL::Module::cells to cells_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/techmap/dfflibmap.cc
View file

@ -388,7 +388,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
log("Mapping DFF cells in module `%s':\n", module->name.c_str());
std::vector<RTLIL::Cell*> cell_list;
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0)
cell_list.push_back(it.second);
}

6
passes/techmap/extract.cc
View file

@ -182,7 +182,7 @@ namespace
std::map<std::pair<RTLIL::Wire*, int>, int> sig_use_count;
if (max_fanout > 0)
for (auto &cell_it : mod->cells)
for (auto &cell_it : mod->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if (!sel || sel->selected(mod, cell))
@ -196,7 +196,7 @@ namespace
}
// create graph nodes from cells
for (auto &cell_it : mod->cells)
for (auto &cell_it : mod->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if (sel && !sel->selected(mod, cell))
@ -253,7 +253,7 @@ namespace
}
// mark external signals (used in non-selected cells)
for (auto &cell_it : mod->cells)
for (auto &cell_it : mod->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if (sel && !sel->selected(mod, cell))

2
passes/techmap/simplemap.cc
View file

@ -439,7 +439,7 @@ struct SimplemapPass : public Pass {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> delete_cells;
for (auto &cell_it : mod_it.second->cells) {
for (auto &cell_it : mod_it.second->cells_) {
if (mappers.count(cell_it.second->type) == 0)
continue;
if (!design->selected(mod_it.second, cell_it.second))

10
passes/techmap/techmap.cc
View file

@ -116,7 +116,7 @@ struct TechmapWorker
std::string orig_cell_name;
if (!flatten_mode)
for (auto &it : tpl->cells)
for (auto &it : tpl->cells_)
if (it.first == "\\_TECHMAP_REPLACE_") {
orig_cell_name = cell->name;
module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name);
@ -180,7 +180,7 @@ struct TechmapWorker
}
}
for (auto &it : tpl->cells)
for (auto &it : tpl->cells_)
{
RTLIL::IdString c_name = it.second->name;
@ -224,15 +224,15 @@ struct TechmapWorker
std::vector<std::string> cell_names;
SigMap sigmap(module);
for (auto &cell_it : module->cells)
for (auto &cell_it : module->cells_)
cell_names.push_back(cell_it.first);
for (auto &cell_name : cell_names)
{
if (module->cells.count(cell_name) == 0)
if (module->cells_.count(cell_name) == 0)
continue;
RTLIL::Cell *cell = module->cells[cell_name];
RTLIL::Cell *cell = module->cells_[cell_name];
if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
continue;