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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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2
passes/sat/freduce.cc
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@ -607,7 +607,7 @@ struct FreduceWorker
batches.push_back(sigmap(it.second).to_sigbit_set());
bits_full_total += it.second->width;
}
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
if (ct.cell_known(it.second->type)) {
std::set<RTLIL::SigBit> inputs, outputs;
for (auto &port : it.second->connections()) {