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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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2
passes/sat/eval.cc
View file

@ -147,7 +147,7 @@ struct VlogHammerReporter
SatGen satgen(&ez, &sigmap);
satgen.model_undef = model_undef;
for (auto &c : module->cells)
for (auto &c : module->cells_)
if (!satgen.importCell(c.second))
log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));

18
passes/sat/expose.cc
View file

@ -82,7 +82,7 @@ static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *modu
SigMap sigmap(module);
SigPool dffsignals;
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
if (ct.cell_known(it.second->type) && it.second->has("\\Q"))
dffsignals.add(sigmap(it.second->get("\\Q")));
}
@ -98,7 +98,7 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info;
SigMap sigmap(module);
for (auto &it : module->cells)
for (auto &it : module->cells_)
{
if (!design->selected(module, it.second))
continue;
@ -371,7 +371,7 @@ struct ExposePass : public Pass {
shared_wires.insert(it.first);
if (flag_evert)
for (auto &it : module->cells)
for (auto &it : module->cells_)
if (design->selected(module, it.second) && consider_cell(design, dff_cells[module], it.second))
shared_cells.insert(it.first);
@ -409,16 +409,16 @@ struct ExposePass : public Pass {
{
RTLIL::Cell *cell;
if (module->cells.count(it) == 0)
if (module->cells_.count(it) == 0)
goto delete_shared_cell;
cell = module->cells.at(it);
cell = module->cells_.at(it);
if (!design->selected(module, cell))
goto delete_shared_cell;
if (!consider_cell(design, dff_cells[module], cell))
goto delete_shared_cell;
if (!compare_cells(first_module->cells.at(it), cell))
if (!compare_cells(first_module->cells_.at(it), cell))
goto delete_shared_cell;
if (0)
@ -475,7 +475,7 @@ struct ExposePass : public Pass {
if (flag_cut)
{
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
if (!ct.cell_known(it.second->type))
continue;
for (auto &conn : it.second->connections_)
@ -503,7 +503,7 @@ struct ExposePass : public Pass {
RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0);
for (auto &cell_name : info.cells) {
RTLIL::Cell *cell = module->cells.at(cell_name);
RTLIL::Cell *cell = module->cells_.at(cell_name);
std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->get("\\Q")).to_sigbit_vector();
for (auto &bit : cell_q_bits)
if (wire_bits_set.count(bit))
@ -571,7 +571,7 @@ struct ExposePass : public Pass {
{
std::vector<RTLIL::Cell*> delete_cells;
for (auto &it : module->cells)
for (auto &it : module->cells_)
{
if (flag_shared) {
if (shared_cells.count(it.first) == 0)

2
passes/sat/freduce.cc
View file

@ -607,7 +607,7 @@ struct FreduceWorker
batches.push_back(sigmap(it.second).to_sigbit_set());
bits_full_total += it.second->width;
}
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
if (ct.cell_known(it.second->type)) {
std::set<RTLIL::SigBit> inputs, outputs;
for (auto &port : it.second->connections()) {

2
passes/sat/sat.cc
View file

@ -317,7 +317,7 @@ struct SatHelper
}
int import_cell_counter = 0;
for (auto &c : module->cells)
for (auto &c : module->cells_)
if (design->selected(module, c.second)) {
// log("Import cell: %s\n", RTLIL::id2cstr(c.first));
if (satgen.importCell(c.second, timestep)) {

4
passes/sat/share.cc
View file

@ -61,7 +61,7 @@ struct ShareWorker
queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end());
for (auto &it : module->cells)
for (auto &it : module->cells_)
if (!fwd_ct.cell_known(it.second->type)) {
std::set<RTLIL::SigBit> &bits = modwalker.cell_inputs[it.second];
queue_bits.insert(bits.begin(), bits.end());
@ -101,7 +101,7 @@ struct ShareWorker
void find_shareable_cells()
{
for (auto &it : module->cells)
for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;