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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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6
passes/opt/opt_const.cc
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@ -37,7 +37,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
SigPool used_signals;
SigPool all_signals;
for (auto &it : module->cells)
for (auto &it : module->cells_)
for (auto &conn : it.second->connections()) {
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
driven_signals.add(sigmap(conn.second));
@ -199,8 +199,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
std::map<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
std::vector<RTLIL::Cell*> cells;
cells.reserve(module->cells.size());
for (auto &cell_it : module->cells)
cells.reserve(module->cells_.size());
for (auto &cell_it : module->cells_)
if (design->selected(module, cell_it.second)) {
if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") &&
cell_it.second->get("\\A").size() == 1 && cell_it.second->get("\\Y").size() == 1)