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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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8
passes/opt/opt_clean.cc
View file

@ -38,7 +38,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> queue, unused;
SigSet<RTLIL::Cell*> wire2driver;
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
for (auto &it2 : cell->connections()) {
if (!ct.cell_input(cell->type, it2.first)) {
@ -155,7 +155,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
SigPool connected_signals;
if (!purge_mode)
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
if (ct_reg.cell_known(cell->type))
for (auto &it2 : cell->connections())
@ -168,7 +168,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
SigMap assign_map(module);
std::set<RTLIL::SigSpec> direct_sigs;
std::set<RTLIL::Wire*> direct_wires;
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
if (ct_all.cell_known(cell->type))
for (auto &it2 : cell->connections())
@ -193,7 +193,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
SigPool used_signals;
SigPool used_signals_nodrivers;
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
for (auto &it2 : cell->connections_) {
assign_map.apply(it2.second);

6
passes/opt/opt_const.cc
View file

@ -37,7 +37,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
SigPool used_signals;
SigPool all_signals;
for (auto &it : module->cells)
for (auto &it : module->cells_)
for (auto &conn : it.second->connections()) {
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
driven_signals.add(sigmap(conn.second));
@ -199,8 +199,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
std::map<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
std::vector<RTLIL::Cell*> cells;
cells.reserve(module->cells.size());
for (auto &cell_it : module->cells)
cells.reserve(module->cells_.size());
for (auto &cell_it : module->cells_)
if (design->selected(module, cell_it.second)) {
if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") &&
cell_it.second->get("\\A").size() == 1 && cell_it.second->get("\\Y").size() == 1)

2
passes/opt/opt_muxtree.cc
View file

@ -83,7 +83,7 @@ struct OptMuxtreeWorker
// .ctrl_sigs
// .input_sigs
// .const_activated
for (auto &cell_it : module->cells)
for (auto &cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")

10
passes/opt/opt_reduce.cc
View file

@ -254,14 +254,14 @@ struct OptReduceWorker
did_something = true;
SigPool mem_wren_sigs;
for (auto &cell_it : module->cells) {
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$mem")
mem_wren_sigs.add(assign_map(cell->get("\\WR_EN")));
if (cell->type == "$memwr")
mem_wren_sigs.add(assign_map(cell->get("\\EN")));
}
for (auto &cell_it : module->cells) {
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->get("\\Q"))))
mem_wren_sigs.add(assign_map(cell->get("\\D")));
@ -270,7 +270,7 @@ struct OptReduceWorker
bool keep_expanding_mem_wren_sigs = true;
while (keep_expanding_mem_wren_sigs) {
keep_expanding_mem_wren_sigs = false;
for (auto &cell_it : module->cells) {
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->get("\\Y")))) {
if (!mem_wren_sigs.check_all(assign_map(cell->get("\\A"))) ||
@ -295,7 +295,7 @@ struct OptReduceWorker
SigSet<RTLIL::Cell*> drivers;
std::set<RTLIL::Cell*> cells;
for (auto &cell_it : module->cells) {
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type != type || !design->selected(module, cell))
continue;
@ -313,7 +313,7 @@ struct OptReduceWorker
std::vector<RTLIL::Cell*> cells;
for (auto &it : module->cells)
for (auto &it : module->cells_)
if ((it.second->type == "$mux" || it.second->type == "$pmux" || it.second->type == "$safe_pmux") && design->selected(module, it.second))
cells.push_back(it.second);

6
passes/opt/opt_rmdff.cc
View file

@ -179,7 +179,7 @@ struct OptRmdffPass : public Pass {
mux_drivers.clear();
std::vector<std::string> dff_list;
for (auto &it : mod_it.second->cells) {
for (auto &it : mod_it.second->cells_) {
if (it.second->type == "$mux" || it.second->type == "$pmux") {
if (it.second->get("\\A").size() == it.second->get("\\B").size())
mux_drivers.insert(assign_map(it.second->get("\\Y")), it.second);
@ -202,8 +202,8 @@ struct OptRmdffPass : public Pass {
}
for (auto &id : dff_list) {
if (mod_it.second->cells.count(id) > 0 &&
handle_dff(mod_it.second, mod_it.second->cells[id]))
if (mod_it.second->cells_.count(id) > 0 &&
handle_dff(mod_it.second, mod_it.second->cells_[id]))
total_count++;
}
}

4
passes/opt/opt_share.cc
View file

@ -248,8 +248,8 @@ struct OptShareWorker
cell_hash_cache.clear();
#endif
std::vector<RTLIL::Cell*> cells;
cells.reserve(module->cells.size());
for (auto &it : module->cells) {
cells.reserve(module->cells_.size());
for (auto &it : module->cells_) {
if (ct.cell_known(it.second->type) && design->selected(module, it.second))
cells.push_back(it.second);
}