mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-10 05:00:52 +00:00
Code Activity

Refactoring: Renamed RTLIL::Module::cells to cells_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
Download patch file Download diff file Expand all files Collapse all files

6
passes/memory/memory_dff.cc
View file

@ -38,7 +38,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
if (bit.wire == NULL)
continue;
for (auto &cell_it : module->cells)
for (auto &cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
@ -120,7 +120,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
for (auto &cell_it : module->cells) {
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$dff") {
RTLIL::SigSpec new_q = cell->get("\\Q");
@ -170,7 +170,7 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only)
{
for (auto &cell_it : module->cells) {
for (auto &cell_it : module->cells_) {
if (!design->selected(module, cell_it.second))
continue;
if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())