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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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2
passes/memory/memory_collect.cc
View file

@ -61,7 +61,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
std::vector<RTLIL::Cell*> del_cells;
std::vector<RTLIL::Cell*> memcells;
for (auto &cell_it : module->cells) {
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name)
memcells.push_back(cell);

6
passes/memory/memory_dff.cc
View file

@ -38,7 +38,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
if (bit.wire == NULL)
continue;
for (auto &cell_it : module->cells)
for (auto &cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
@ -120,7 +120,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
for (auto &cell_it : module->cells) {
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$dff") {
RTLIL::SigSpec new_q = cell->get("\\Q");
@ -170,7 +170,7 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only)
{
for (auto &cell_it : module->cells) {
for (auto &cell_it : module->cells_) {
if (!design->selected(module, cell_it.second))
continue;
if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())

2
passes/memory/memory_map.cc
View file

@ -295,7 +295,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
{
std::vector<RTLIL::Cell*> cells;
for (auto &it : module->cells)
for (auto &it : module->cells_)
if (it.second->type == "$mem" && design->selected(module, it.second))
cells.push_back(it.second);
for (auto cell : cells)

4
passes/memory/memory_share.cc
View file

@ -143,7 +143,7 @@ struct MemoryShareWorker
non_feedback_nets.insert(bits.begin(), bits.end());
}
for (auto cell_it : module->cells)
for (auto cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
bool ignore_data_port = false;
@ -650,7 +650,7 @@ struct MemoryShareWorker
std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex;
sigmap_xmux = sigmap;
for (auto &it : module->cells)
for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;

4
passes/memory/memory_unpack.cc
View file

@ -80,11 +80,11 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
{
std::vector<RTLIL::IdString> memcells;
for (auto &cell_it : module->cells)
for (auto &cell_it : module->cells_)
if (cell_it.second->type == "$mem" && design->selected(module, cell_it.second))
memcells.push_back(cell_it.first);
for (auto &it : memcells)
handle_memory(module, module->cells.at(it));
handle_memory(module, module->cells_.at(it));
}
struct MemoryUnpackPass : public Pass {