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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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6
passes/hierarchy/submod.cc
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@ -87,7 +87,7 @@ struct SubmodWorker
flag_signal(conn.second, true, true, true, false, false);
}
}
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second;
if (submod.cells.count(cell) > 0)
continue;
@ -215,7 +215,7 @@ struct SubmodWorker
for (auto &it : module->wires_)
it.second->attributes.erase("\\submod");
for (auto &it : module->cells)
for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].bits.size() == 0) {
@ -239,7 +239,7 @@ struct SubmodWorker
}
else
{
for (auto &it : module->cells)
for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
if (!design->selected(module, cell))