3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-26 21:16:03 +00:00

Refactoring: Renamed RTLIL::Module::cells to cells_

This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions

View file

@ -290,7 +290,7 @@ struct FsmOptPass : public Pass {
for (auto &mod_it : design->modules) {
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells)
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" and design->selected(mod_it.second, cell_it.second))
FsmData::optimize_fsm(cell_it.second, mod_it.second);
}