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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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2
passes/fsm/fsm_info.cc
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@ -45,7 +45,7 @@ struct FsmInfoPass : public Pass {
for (auto &mod_it : design->modules)
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells)
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
log("\n");
log("FSM `%s' from module `%s':\n", cell_it.second->name.c_str(), mod_it.first.c_str());