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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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4
passes/fsm/fsm_expand.cc
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@ -205,7 +205,7 @@ struct FsmExpand
assign_map.set(module);
ct.setup_internals();
for (auto &cell_it : module->cells) {
for (auto &cell_it : module->cells_) {
RTLIL::Cell *c = cell_it.second;
if (ct.cell_known(c->type) && design->selected(mod, c))
for (auto &p : c->connections()) {
@ -262,7 +262,7 @@ struct FsmExpandPass : public Pass {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> fsm_cells;
for (auto &cell_it : mod_it.second->cells)
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
fsm_cells.push_back(cell_it.second);
for (auto c : fsm_cells) {