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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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2
passes/fsm/fsm_detect.cc
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@ -159,7 +159,7 @@ struct FsmDetectPass : public Pass {
sig2driver.clear();
sig2user.clear();
sig_at_port.clear();
for (auto &cell_it : module->cells)
for (auto &cell_it : module->cells_)
for (auto &conn_it : cell_it.second->connections()) {
if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
RTLIL::SigSpec sig = conn_it.second;