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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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2
passes/fsm/fsm_detect.cc
View file

@ -159,7 +159,7 @@ struct FsmDetectPass : public Pass {
sig2driver.clear();
sig2user.clear();
sig_at_port.clear();
for (auto &cell_it : module->cells)
for (auto &cell_it : module->cells_)
for (auto &conn_it : cell_it.second->connections()) {
if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
RTLIL::SigSpec sig = conn_it.second;

4
passes/fsm/fsm_expand.cc
View file

@ -205,7 +205,7 @@ struct FsmExpand
assign_map.set(module);
ct.setup_internals();
for (auto &cell_it : module->cells) {
for (auto &cell_it : module->cells_) {
RTLIL::Cell *c = cell_it.second;
if (ct.cell_known(c->type) && design->selected(mod, c))
for (auto &p : c->connections()) {
@ -262,7 +262,7 @@ struct FsmExpandPass : public Pass {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> fsm_cells;
for (auto &cell_it : mod_it.second->cells)
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
fsm_cells.push_back(cell_it.second);
for (auto c : fsm_cells) {

2
passes/fsm/fsm_export.cc
View file

@ -176,7 +176,7 @@ struct FsmExportPass : public Pass {
for (auto &mod_it : design->modules)
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells)
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
attr_it = cell_it.second->attributes.find("\\fsm_export");
if (!flag_noauto || (attr_it != cell_it.second->attributes.end())) {

10
passes/fsm/fsm_extract.cc
View file

@ -53,7 +53,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
std::set<sig2driver_entry_t> cellport_list;
sig2driver.find(sig, cellport_list);
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cells.at(cellport.first);
RTLIL::Cell *cell = module->cells_.at(cellport.first);
if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || cellport.second != "\\Y") {
log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
return false;
@ -179,7 +179,7 @@ static void extract_fsm(RTLIL::Wire *wire)
std::set<sig2driver_entry_t> cellport_list;
sig2driver.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cells.at(cellport.first);
RTLIL::Cell *cell = module->cells_.at(cellport.first);
if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q")
continue;
log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
@ -223,7 +223,7 @@ static void extract_fsm(RTLIL::Wire *wire)
cellport_list.clear();
sig2trigger.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cells.at(cellport.first);
RTLIL::Cell *cell = module->cells_.at(cellport.first);
RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y"));
@ -293,7 +293,7 @@ static void extract_fsm(RTLIL::Wire *wire)
cellport_list.clear();
sig2driver.find(ctrl_out, cellport_list);
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cells.at(cellport.first);
RTLIL::Cell *cell = module->cells_.at(cellport.first);
RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second));
RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++), unconn_sig.size());
@ -340,7 +340,7 @@ struct FsmExtractPass : public Pass {
sig2driver.clear();
sig2trigger.clear();
for (auto &cell_it : module->cells)
for (auto &cell_it : module->cells_)
for (auto &conn_it : cell_it.second->connections()) {
if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
RTLIL::SigSpec sig = conn_it.second;

2
passes/fsm/fsm_info.cc
View file

@ -45,7 +45,7 @@ struct FsmInfoPass : public Pass {
for (auto &mod_it : design->modules)
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells)
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
log("\n");
log("FSM `%s' from module `%s':\n", cell_it.second->name.c_str(), mod_it.first.c_str());

2
passes/fsm/fsm_map.cc
View file

@ -313,7 +313,7 @@ struct FsmMapPass : public Pass {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> fsm_cells;
for (auto &cell_it : mod_it.second->cells)
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
fsm_cells.push_back(cell_it.second);
for (auto cell : fsm_cells)

2
passes/fsm/fsm_opt.cc
View file

@ -290,7 +290,7 @@ struct FsmOptPass : public Pass {
for (auto &mod_it : design->modules) {
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells)
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" and design->selected(mod_it.second, cell_it.second))
FsmData::optimize_fsm(cell_it.second, mod_it.second);
}

2
passes/fsm/fsm_recode.cc
View file

@ -146,7 +146,7 @@ struct FsmRecodePass : public Pass {
for (auto &mod_it : design->modules)
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells)
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
fsm_recode(cell_it.second, mod_it.second, fm_set_fsm_file, default_encoding);