mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-09 20:50:51 +00:00
Code Activity

Refactoring: Renamed RTLIL::Module::cells to cells_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/cmds/splice.cc
View file

@ -158,7 +158,7 @@ struct SpliceWorker
driven_bits.push_back(RTLIL::State::Sm);
}
for (auto &it : module->cells)
for (auto &it : module->cells_)
for (auto &conn : it.second->connections())
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) {
RTLIL::SigSpec sig = sigmap(conn.second);
@ -179,7 +179,7 @@ struct SpliceWorker
if (design->selected(module, it.second))
selected_bits.add(sigmap(it.second));
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
if (!sel_by_wire && !design->selected(module, it.second))
continue;
for (auto &conn : it.second->connections_)