mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-08 04:01:25 +00:00
Code Activity

Refactoring: Renamed RTLIL::Module::cells to cells_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/cmds/setattr.cc
View file

@ -119,7 +119,7 @@ struct SetattrPass : public Pass {
if (design->selected(module, it.second))
do_setunset(it.second->attributes, setunset_list);
for (auto &it : module->cells)
for (auto &it : module->cells_)
if (design->selected(module, it.second))
do_setunset(it.second->attributes, setunset_list);
@ -171,7 +171,7 @@ struct SetparamPass : public Pass {
if (!design->selected(module))
continue;
for (auto &it : module->cells)
for (auto &it : module->cells_)
if (design->selected(module, it.second))
do_setunset(it.second->parameters, setunset_list);
}