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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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2
passes/cmds/scatter.cc
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@ -48,7 +48,7 @@ struct ScatterPass : public Pass {
if (!design->selected(mod_it.second))
continue;
for (auto &c : mod_it.second->cells)
for (auto &c : mod_it.second->cells_)
for (auto &p : c.second->connections_)
{
RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size());