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Refactoring: Renamed RTLIL::Module::cells to cells_

This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions

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@ -67,7 +67,7 @@ struct ConnwrappersWorker
std::map<RTLIL::SigBit, std::pair<bool, RTLIL::SigSpec>> extend_map;
SigMap sigmap(module);
for (auto &it : module->cells)
for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
@ -102,7 +102,7 @@ struct ConnwrappersWorker
}
}
for (auto &it : module->cells)
for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;