mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-24 14:53:42 +00:00
Code Activity

Refactoring: Renamed RTLIL::Module::cells to cells_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
Download patch file Download diff file Expand all files Collapse all files

4
kernel/rtlil.h
View file

@ -282,7 +282,7 @@ public:
std::set<RTLIL::IdString> avail_parameters;
std::map<RTLIL::IdString, RTLIL::Wire*> wires_;
std::map<RTLIL::IdString, RTLIL::Memory*> memories;
std::map<RTLIL::IdString, RTLIL::Cell*> cells;
std::map<RTLIL::IdString, RTLIL::Cell*> cells_;
std::map<RTLIL::IdString, RTLIL::Process*> processes;
std::vector<RTLIL::SigSig> connections_;
RTLIL_ATTRIBUTE_MEMBERS
@ -719,7 +719,7 @@ struct RTLIL::Process {
template<typename T>
void RTLIL::Module::rewrite_sigspecs(T functor)
{
for (auto &it : cells)
for (auto &it : cells_)
it.second->rewrite_sigspecs(functor);
for (auto &it : processes)
it.second->rewrite_sigspecs(functor);