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Remove delay targets doc

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Eddie Hung 2019-12-30 16:11:42 -08:00
parent 0735572934
commit 4c3f517425
1 changed files with 0 additions and 9 deletions
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9
passes/techmap/abc9.cc
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@ -825,15 +825,6 @@ struct Abc9Pass : public Pass {
log("design as an XAIGER file with write_xaiger and then load that into ABC externally\n"); log("design as an XAIGER file with write_xaiger and then load that into ABC externally\n");
log("if you want to use ABC to convert your design into another format.\n"); log("if you want to use ABC to convert your design into another format.\n");
log("\n"); log("\n");
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("Delay targets can also be specified on a per clock basis by attaching a\n");
log("'(* abc9_period = <int> *)' attribute onto clock wires (specifically, onto wires\n");
log("that appear inside any special '$abc9_clock' wires inserted by abc9_map.v). This\n");
log("can be achieved by modifying the source directly, or through a `setattr`\n");
log("invocation. Since such attributes cannot yet be propagated through a\n");
log("hierarchical design (whether or not it has been uniquified) it is recommended\n");
log("that the design be flattened when using this feature.\n");
log("\n");
log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n"); log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
log("\n"); log("\n");
} }