mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-29 14:30:08 +00:00
shiftx2mux: fix select out of bounds
This commit is contained in:
parent
505557e93e
commit
4c1d3a126d
3 changed files with 14 additions and 2 deletions
|
@ -108,3 +108,14 @@ design -import gate -as gate
|
|||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module top(input [6:0] A, input [1:0] B, output [1:0] Y);
|
||||
wire [7:0] AA = {1'bx, A};
|
||||
assign Y = AA[B*2 +: 2];
|
||||
endmodule
|
||||
EOT
|
||||
opt
|
||||
wreduce
|
||||
equiv_opt techmap
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue