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sv: Improve handling of wildcard port connections

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-11-22 15:07:55 +00:00
parent ebe1d7d5ab
commit 4bfd2ef4f3
3 changed files with 9 additions and 7 deletions
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2
frontends/verilog/verilog_lexer.l
View file

@ -431,7 +431,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
"+:" { return TOK_POS_INDEXED; } "+:" { return TOK_POS_INDEXED; }
"-:" { return TOK_NEG_INDEXED; } "-:" { return TOK_NEG_INDEXED; }
".*" { return TOK_AUTOCONNECT_ALL; } ".*" { return TOK_WILDCARD_CONNECT; }
[-+]?[=*]> { [-+]?[=*]> {
if (!specify_mode) REJECT; if (!specify_mode) REJECT;

8
frontends/verilog/verilog_parser.y
View file

@ -138,7 +138,7 @@ struct specify_rise_fall {
%token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
%token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
%token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_AUTOCONNECT_ALL %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
%token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
@ -1581,8 +1581,10 @@ cell_port:
delete $3; delete $3;
free_attr($1); free_attr($1);
} | } |
attr TOK_AUTOCONNECT_ALL { attr TOK_WILDCARD_CONNECT {
astbuf2->attributes[ID(implicit_port_conns)] = AstNode::mkconst_int(1, false); if (!sv_mode)
frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
astbuf2->attributes[ID(wildcard_port_conns)] = AstNode::mkconst_int(1, false);
}; };
always_comb_or_latch: always_comb_or_latch:

6
passes/hierarchy/hierarchy.cc
View file

@ -992,7 +992,7 @@ struct HierarchyPass : public Pass {
if (wire->port_input && wire->attributes.count("\\defaultvalue")) if (wire->port_input && wire->attributes.count("\\defaultvalue"))
defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue"); defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue");
} }
// Process SV implicit port connections // Process SV implicit wildcard port connections
std::set<Module*> blackbox_derivatives; std::set<Module*> blackbox_derivatives;
std::vector<Module*> design_modules = design->modules(); std::vector<Module*> design_modules = design->modules();
@ -1000,7 +1000,7 @@ struct HierarchyPass : public Pass {
{ {
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (!cell->get_bool_attribute(ID(implicit_port_conns))) if (!cell->get_bool_attribute(ID(wildcard_port_conns)))
continue; continue;
Module *m = design->module(cell->type); Module *m = design->module(cell->type);
@ -1042,7 +1042,7 @@ struct HierarchyPass : public Pass {
RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
cell->setPort(wire->name, parent_wire); cell->setPort(wire->name, parent_wire);
} }
cell->attributes.erase(ID(implicit_port_conns)); cell->attributes.erase(ID(wildcard_port_conns));
} }
} }