From 7ff5d6d30ae9f48376f0c6a98d8a5fa0831faf77 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 18 Nov 2019 13:58:03 +0000 Subject: [PATCH 1/6] memory_collect: Copy attr from RTLIL::Memory to cell Signed-off-by: David Shah --- passes/memory/memory_collect.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 6acbce62f..9dcb3f024 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -218,6 +218,10 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) mem->setPort("\\RD_DATA", sig_rd_data); mem->setPort("\\RD_EN", sig_rd_en); + // Copy attributes from RTLIL memory to $mem + for (auto attr : memory->attributes) + mem->attributes[attr.first] = attr.second; + for (auto c : memcells) module->remove(c); From 222e199b7342818cc4265e21ff8910ceb42fb421 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 26 Nov 2019 21:26:30 -0800 Subject: [PATCH 2/6] Add testcase derived from fastfir_dynamictaps benchmark --- tests/arch/xilinx/dsp_fastfir.ys | 68 ++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 tests/arch/xilinx/dsp_fastfir.ys diff --git a/tests/arch/xilinx/dsp_fastfir.ys b/tests/arch/xilinx/dsp_fastfir.ys new file mode 100644 index 000000000..30e74a01b --- /dev/null +++ b/tests/arch/xilinx/dsp_fastfir.ys @@ -0,0 +1,68 @@ +read_verilog < Date: Tue, 26 Nov 2019 21:26:53 -0800 Subject: [PATCH 3/6] Check for either sign or zero extension for postAdd packing --- passes/pmgen/xilinx_dsp.pmg | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 0ba529011..5d3b9c2eb 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -347,9 +347,9 @@ match postAdd index port(postAdd, AB)[0] === sigP[0] filter GetSize(port(postAdd, AB)) >= GetSize(sigP) filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP - // Check that remainder of AB is a sign-extension - define AB_SIGNED (param(postAdd, AB == \A ? \A_SIGNED : \B_SIGNED).as_bool()) - filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(AB_SIGNED ? sigP[GetSize(sigP)-1] : State::S0, GetSize(port(postAdd, AB))-GetSize(sigP)) + // Check that remainder of AB is a sign- or zero-extension + filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP)) || port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(State::S0, GetSize(port(postAdd, AB))-GetSize(sigP)) + set postAddAB AB optional endmatch From 4a0198128eb966d00c24bd6938625892e7fd4b95 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 26 Nov 2019 22:51:16 -0800 Subject: [PATCH 4/6] Add citation --- tests/arch/xilinx/dsp_fastfir.ys | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/arch/xilinx/dsp_fastfir.ys b/tests/arch/xilinx/dsp_fastfir.ys index 30e74a01b..b205d42c1 100644 --- a/tests/arch/xilinx/dsp_fastfir.ys +++ b/tests/arch/xilinx/dsp_fastfir.ys @@ -1,4 +1,5 @@ read_verilog < Date: Wed, 27 Nov 2019 00:46:21 +0100 Subject: [PATCH 5/6] opt_share: Fix handling of fine cells. Fixes #1525. --- passes/opt/opt_share.cc | 15 +++++++++++---- tests/opt/bug1525.ys | 13 +++++++++++++ 2 files changed, 24 insertions(+), 4 deletions(-) create mode 100644 tests/opt/bug1525.ys diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 2c456705c..f59f978a6 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -83,7 +83,9 @@ struct ExtSigSpec { bool operator==(const ExtSigSpec &other) const { return is_signed == other.is_signed && sign == other.sign && sig == other.sig && semantics == other.semantics; } }; -#define BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($and), ID($or), ID($xor), ID($xnor) +#define FINE_BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_) + +#define BITWISE_OPS FINE_BITWISE_OPS, ID($and), ID($or), ID($xor), ID($xnor) #define REDUCTION_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($reduce_nand) @@ -250,14 +252,19 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< shared_op->setPort(ID(CO), alu_co.extract(0, conn_width)); } - shared_op->setParam(ID(Y_WIDTH), conn_width); + bool is_fine = shared_op->type.in(FINE_BITWISE_OPS); + + if (!is_fine) + shared_op->setParam(ID(Y_WIDTH), conn_width); if (decode_port(shared_op, ID::A, &assign_map) == operand) { shared_op->setPort(ID::B, mux_to_oper); - shared_op->setParam(ID(B_WIDTH), max_width); + if (!is_fine) + shared_op->setParam(ID(B_WIDTH), max_width); } else { shared_op->setPort(ID::A, mux_to_oper); - shared_op->setParam(ID(A_WIDTH), max_width); + if (!is_fine) + shared_op->setParam(ID(A_WIDTH), max_width); } } diff --git a/tests/opt/bug1525.ys b/tests/opt/bug1525.ys new file mode 100644 index 000000000..972bc0ac7 --- /dev/null +++ b/tests/opt/bug1525.ys @@ -0,0 +1,13 @@ +read_verilog << EOF +module top(...); +input A1, A2, B, S; +output O; + +assign O = S ? (A1 & B) : (A2 & B); + +endmodule +EOF + +simplemap +opt_share +dump From de3476cc233c1c78d3e956aa7e9bd1003ac37f66 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 26 Nov 2019 23:08:14 -0800 Subject: [PATCH 6/6] No need for -abc9 --- tests/arch/xilinx/dsp_fastfir.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/arch/xilinx/dsp_fastfir.ys b/tests/arch/xilinx/dsp_fastfir.ys index b205d42c1..0067a822b 100644 --- a/tests/arch/xilinx/dsp_fastfir.ys +++ b/tests/arch/xilinx/dsp_fastfir.ys @@ -63,7 +63,7 @@ module fastfir_dynamictaps(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_re endmodule EOT -synth_xilinx -abc9 +synth_xilinx cd fastfir_dynamictaps select -assert-count 2 t:DSP48E1 select -assert-none t:* t:DSP48E1 %d t:BUFG %d