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Merge pull request #5095 from YosysHQ/emil/one-bit-width

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rtlil: enable single-bit vector wires
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Emil J 2025-05-23 15:55:45 +02:00 • committed by GitHub
commit 4b8d42d22c
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6 changed files with 46 additions and 0 deletions
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6
frontends/ast/simplify.cc
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@ -2086,6 +2086,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
std::swap(range_left, range_right);
range_swapped = force_upto;
}
if (range_left == range_right)
set_attribute(ID::single_bit_vector, mkconst_int(1, false));
}
} else {
if (!range_valid)
@ -2094,6 +2096,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
range_swapped = false;
range_left = 0;
range_right = 0;
if (attributes.count(ID::single_bit_vector)) {
delete attributes[ID::single_bit_vector];
attributes.erase(ID::single_bit_vector);
}
}
}