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https://github.com/YosysHQ/yosys
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SigSpec refactoring: using the accessor functions everywhere
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parent
16e5ae0b92
commit
4b4048bc5f
62 changed files with 800 additions and 800 deletions
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@ -100,7 +100,7 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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}
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}
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if (sig_c.is_fully_const() && (!sig_r.__width || !has_init)) {
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if (sig_c.is_fully_const() && (!sig_r.size() || !has_init)) {
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if (val_rv.bits.size() == 0)
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val_rv = val_init;
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RTLIL::SigSig conn(sig_q, val_rv);
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@ -108,26 +108,26 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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goto delete_dff;
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}
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if (sig_d.is_fully_undef() && sig_r.__width && !has_init) {
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if (sig_d.is_fully_undef() && sig_r.size() && !has_init) {
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RTLIL::SigSig conn(sig_q, val_rv);
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mod->connections.push_back(conn);
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goto delete_dff;
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}
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if (sig_d.is_fully_undef() && !sig_r.__width && has_init) {
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if (sig_d.is_fully_undef() && !sig_r.size() && has_init) {
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RTLIL::SigSig conn(sig_q, val_init);
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mod->connections.push_back(conn);
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goto delete_dff;
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}
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if (sig_d.is_fully_const() && !sig_r.__width && !has_init) {
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if (sig_d.is_fully_const() && !sig_r.size() && !has_init) {
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RTLIL::SigSig conn(sig_q, sig_d);
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mod->connections.push_back(conn);
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goto delete_dff;
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}
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if (sig_d == sig_q && !(sig_r.__width && has_init)) {
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if (sig_r.__width) {
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if (sig_d == sig_q && !(sig_r.size() && has_init)) {
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if (sig_r.size()) {
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RTLIL::SigSig conn(sig_q, val_rv);
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mod->connections.push_back(conn);
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}
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@ -182,7 +182,7 @@ struct OptRmdffPass : public Pass {
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std::vector<std::string> dff_list;
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for (auto &it : mod_it.second->cells) {
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if (it.second->type == "$mux" || it.second->type == "$pmux") {
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if (it.second->connections.at("\\A").__width == it.second->connections.at("\\B").__width)
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if (it.second->connections.at("\\A").size() == it.second->connections.at("\\B").size())
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mux_drivers.insert(assign_map(it.second->connections.at("\\Y")), it.second);
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continue;
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}
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